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[RISCV] Use range-based for loops in RISCVOptWInstrs. NFC #69647

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Merged
merged 1 commit into from
Oct 20, 2023
Merged

[RISCV] Use range-based for loops in RISCVOptWInstrs. NFC #69647

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18 changes: 7 additions & 11 deletions llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -602,25 +602,23 @@ bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,

bool MadeChange = false;
for (MachineBasicBlock &MBB : MF) {
for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
MachineInstr *MI = &*I++;

for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
// We're looking for the sext.w pattern ADDIW rd, rs1, 0.
if (!RISCV::isSEXT_W(*MI))
if (!RISCV::isSEXT_W(MI))
continue;

Register SrcReg = MI->getOperand(1).getReg();
Register SrcReg = MI.getOperand(1).getReg();

SmallPtrSet<MachineInstr *, 4> FixableDefs;

// If all users only use the lower bits, this sext.w is redundant.
// Or if all definitions reaching MI sign-extend their output,
// then sext.w is redundant.
if (!hasAllWUsers(*MI, ST, MRI) &&
if (!hasAllWUsers(MI, ST, MRI) &&
!isSignExtendedW(SrcReg, ST, MRI, FixableDefs))
continue;

Register DstReg = MI->getOperand(0).getReg();
Register DstReg = MI.getOperand(0).getReg();
if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
continue;

Expand All @@ -638,7 +636,7 @@ bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,
LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
MRI.replaceRegWith(DstReg, SrcReg);
MRI.clearKillFlags(SrcReg);
MI->eraseFromParent();
MI.eraseFromParent();
++NumRemovedSExtW;
MadeChange = true;
}
Expand All @@ -656,9 +654,7 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,

bool MadeChange = false;
for (MachineBasicBlock &MBB : MF) {
for (auto I = MBB.begin(), IE = MBB.end(); I != IE; ++I) {
MachineInstr &MI = *I;

for (MachineInstr &MI : MBB) {
unsigned Opc;
switch (MI.getOpcode()) {
default:
Expand Down