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[RISCV][GISel] Add instruction selection for G_FADD/G_FSUB/G_FMUL/G_FDIV with F/D extensions. #69808

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Merged
merged 1 commit into from
Oct 25, 2023
Merged

[RISCV][GISel] Add instruction selection for G_FADD/G_FSUB/G_FMUL/G_FDIV with F/D extensions. #69808

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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -450,6 +450,13 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
return &RISCV::GPRRegClass;
}

if (RB.getID() == RISCV::FPRRegBankID) {
if (Ty.getSizeInBits() == 32)
return &RISCV::FPR32RegClass;
if (Ty.getSizeInBits() == 64)
return &RISCV::FPR64RegClass;
}

// TODO: Non-GPR register classes.
return nullptr;
}
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198 changes: 198 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
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@@ -0,0 +1,198 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: fadd_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fadd_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[COPY1]], 7
; CHECK-NEXT: $f10_f = COPY [[FADD_S]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%2:fprb(s32) = G_FADD %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fsub_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fsub_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FSUB_S:%[0-9]+]]:fpr32 = nofpexcept FSUB_S [[COPY]], [[COPY1]], 7
; CHECK-NEXT: $f10_f = COPY [[FSUB_S]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%2:fprb(s32) = G_FSUB %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fmul_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fmul_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FMUL_S:%[0-9]+]]:fpr32 = nofpexcept FMUL_S [[COPY]], [[COPY1]], 7
; CHECK-NEXT: $f10_f = COPY [[FMUL_S]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%2:fprb(s32) = G_FMUL %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fdiv_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fdiv_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FDIV_S:%[0-9]+]]:fpr32 = nofpexcept FDIV_S [[COPY]], [[COPY1]], 7
; CHECK-NEXT: $f10_f = COPY [[FDIV_S]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%2:fprb(s32) = G_FDIV %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fadd_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fadd_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7
; CHECK-NEXT: $f10_d = COPY [[FADD_D]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%2:fprb(s64) = G_FADD %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
---
name: fsub_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fsub_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FSUB_D:%[0-9]+]]:fpr64 = nofpexcept FSUB_D [[COPY]], [[COPY1]], 7
; CHECK-NEXT: $f10_d = COPY [[FSUB_D]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%2:fprb(s64) = G_FSUB %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
---
name: fmul_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fmul_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FMUL_D:%[0-9]+]]:fpr64 = nofpexcept FMUL_D [[COPY]], [[COPY1]], 7
; CHECK-NEXT: $f10_d = COPY [[FMUL_D]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%2:fprb(s64) = G_FMUL %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
---
name: fdiv_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fdiv_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FDIV_D:%[0-9]+]]:fpr64 = nofpexcept FDIV_D [[COPY]], [[COPY1]], 7
; CHECK-NEXT: $f10_d = COPY [[FDIV_D]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%2:fprb(s64) = G_FDIV %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...