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[GISel] Remove BitVector from RegBank. Use tablegen CoverageData tables directly. NFC #71105

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Merged
merged 1 commit into from
Nov 3, 2023
Merged

[GISel] Remove BitVector from RegBank. Use tablegen CoverageData tables directly. NFC #71105

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9 changes: 6 additions & 3 deletions llvm/include/llvm/CodeGen/RegisterBank.h
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@
#ifndef LLVM_CODEGEN_REGISTERBANK_H
#define LLVM_CODEGEN_REGISTERBANK_H

#include "llvm/ADT/BitVector.h"
#include <cstdint>

namespace llvm {
// Forward declarations.
Expand All @@ -28,15 +28,18 @@ class TargetRegisterInfo;
class RegisterBank {
private:
unsigned ID;
unsigned NumRegClasses;
const char *Name;
BitVector ContainedRegClasses;
const uint32_t *CoveredClasses;

/// Only the RegisterBankInfo can initialize RegisterBank properly.
friend RegisterBankInfo;

public:
RegisterBank(unsigned ID, const char *Name, const uint32_t *CoveredClasses,
unsigned NumRegClasses);
unsigned NumRegClasses)
: ID(ID), NumRegClasses(NumRegClasses), Name(Name),
CoveredClasses(CoveredClasses) {}

/// Get the identifier of this register bank.
unsigned getID() const { return ID; }
Expand Down
22 changes: 9 additions & 13 deletions llvm/lib/CodeGen/RegisterBank.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -20,14 +20,6 @@

using namespace llvm;

RegisterBank::RegisterBank(unsigned ID, const char *Name,
const uint32_t *CoveredClasses,
unsigned NumRegClasses)
: ID(ID), Name(Name) {
ContainedRegClasses.resize(NumRegClasses);
ContainedRegClasses.setBitsInMask(CoveredClasses);
}

bool RegisterBank::verify(const RegisterBankInfo &RBI,
const TargetRegisterInfo &TRI) const {
for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
Expand Down Expand Up @@ -58,7 +50,7 @@ bool RegisterBank::verify(const RegisterBankInfo &RBI,
}

bool RegisterBank::covers(const TargetRegisterClass &RC) const {
return ContainedRegClasses.test(RC.getID());
return (CoveredClasses[RC.getID() / 32] & (1U << RC.getID() % 32)) != 0;
}

bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
Expand All @@ -81,14 +73,18 @@ void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
OS << getName();
if (!IsForDebug)
return;

unsigned Count = 0;
for (int i = 0, e = ((NumRegClasses + 31) / 32); i != e; ++i)
Count += llvm::popcount(CoveredClasses[i]);

OS << "(ID:" << getID() << ")\n"
<< "Number of Covered register classes: " << ContainedRegClasses.count()
<< '\n';
<< "Number of Covered register classes: " << Count << '\n';
// Print all the subclasses if we can.
// This register classes may not be properly initialized yet.
if (!TRI || ContainedRegClasses.empty())
if (!TRI || NumRegClasses == 0)
return;
assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
assert(NumRegClasses == TRI->getNumRegClasses() &&
"TRI does not match the initialization process?");
OS << "Covered register classes:\n";
ListSeparator LS;
Expand Down