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[RISCV] Remove setJumpIsExpensive(). #74647

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Merged
merged 1 commit into from
Dec 13, 2023
Merged

[RISCV] Remove setJumpIsExpensive(). #74647

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3 changes: 0 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1363,9 +1363,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());

// Jumps are expensive, compared to logic
setJumpIsExpensive();

setTargetDAGCombine({ISD::INTRINSIC_VOID, ISD::INTRINSIC_W_CHAIN,
ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND,
ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT});
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36 changes: 19 additions & 17 deletions llvm/test/CodeGen/RISCV/double-previous-failure.ll
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Expand Up @@ -31,16 +31,17 @@ define i32 @main() nounwind {
; RV32IFD-NEXT: fld fa5, 0(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IFD-NEXT: fld fa3, %lo(.LCPI1_1)(a0)
; RV32IFD-NEXT: flt.d a0, fa5, fa4
; RV32IFD-NEXT: flt.d a1, fa3, fa5
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: beqz a0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: call abort@plt
; RV32IFD-NEXT: .LBB1_2: # %if.end
; RV32IFD-NEXT: bnez a0, .LBB1_3
; RV32IFD-NEXT: # %bb.1: # %entry
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_1)(a0)
; RV32IFD-NEXT: flt.d a0, fa4, fa5
; RV32IFD-NEXT: bnez a0, .LBB1_3
; RV32IFD-NEXT: # %bb.2: # %if.end
; RV32IFD-NEXT: call exit@plt
; RV32IFD-NEXT: .LBB1_3: # %if.then
; RV32IFD-NEXT: call abort@plt
;
; RV32IZFINXZDINX-LABEL: main:
; RV32IZFINXZDINX: # %bb.0: # %entry
Expand All @@ -56,17 +57,18 @@ define i32 @main() nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI1_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a4)
; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a2
; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a0, .LBB1_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.then
; RV32IZFINXZDINX-NEXT: call abort@plt
; RV32IZFINXZDINX-NEXT: .LBB1_2: # %if.end
; RV32IZFINXZDINX-NEXT: bnez a2, .LBB1_3
; RV32IZFINXZDINX-NEXT: # %bb.1: # %entry
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_1+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a2)
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3
; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end
; RV32IZFINXZDINX-NEXT: call exit@plt
; RV32IZFINXZDINX-NEXT: .LBB1_3: # %if.then
; RV32IZFINXZDINX-NEXT: call abort@plt
entry:
%call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01
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26 changes: 14 additions & 12 deletions llvm/test/CodeGen/RISCV/select-and.ll
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Expand Up @@ -40,14 +40,15 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: beqz a0, .LBB1_2
; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: beqz a0, .LBB1_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: beqz a1, .LBB1_3
; RV32I-NEXT: # %bb.2: # %if.then
; RV32I-NEXT: call both@plt
; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2: # %if.else
; RV32I-NEXT: j .LBB1_4
; RV32I-NEXT: .LBB1_3: # %if.else
; RV32I-NEXT: call neither@plt
; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: .LBB1_4: # %if.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -56,14 +57,15 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: beqz a0, .LBB1_2
; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: beqz a0, .LBB1_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: beqz a1, .LBB1_3
; RV64I-NEXT: # %bb.2: # %if.then
; RV64I-NEXT: call both@plt
; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2: # %if.else
; RV64I-NEXT: j .LBB1_4
; RV64I-NEXT: .LBB1_3: # %if.else
; RV64I-NEXT: call neither@plt
; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: .LBB1_4: # %if.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
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30 changes: 16 additions & 14 deletions llvm/test/CodeGen/RISCV/select-or.ll
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Expand Up @@ -40,14 +40,15 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: beqz a0, .LBB1_2
; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: call either@plt
; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2: # %if.else
; RV32I-NEXT: bnez a0, .LBB1_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: bnez a1, .LBB1_3
; RV32I-NEXT: # %bb.2: # %if.else
; RV32I-NEXT: call neither@plt
; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: j .LBB1_4
; RV32I-NEXT: .LBB1_3: # %if.then
; RV32I-NEXT: call either@plt
; RV32I-NEXT: .LBB1_4: # %if.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -56,14 +57,15 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: beqz a0, .LBB1_2
; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call either@plt
; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2: # %if.else
; RV64I-NEXT: bnez a0, .LBB1_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: bnez a1, .LBB1_3
; RV64I-NEXT: # %bb.2: # %if.else
; RV64I-NEXT: call neither@plt
; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: j .LBB1_4
; RV64I-NEXT: .LBB1_3: # %if.then
; RV64I-NEXT: call either@plt
; RV64I-NEXT: .LBB1_4: # %if.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
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