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[RISCV] Bump zicfilp to 0.4 #75134

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Merged
merged 1 commit into from
Dec 13, 2023
Merged

[RISCV] Bump zicfilp to 0.4 #75134

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6 changes: 3 additions & 3 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -1056,12 +1056,12 @@
// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 8000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zicfilp0p2 -x c -E -dM %s \
// RUN: -march=rv32i_zicfilp0p4 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zicfilp0p2 -x c -E -dM %s \
// RUN: -march=rv64i_zicfilp0p4 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
// CHECK-ZICFILP-EXT: __riscv_zicfilp 2000{{$}}
// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
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2 changes: 1 addition & 1 deletion llvm/docs/RISCVUsage.rst
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Expand Up @@ -197,7 +197,7 @@ The primary goal of experimental support is to assist in the process of ratifica
LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.

``experimental-zicfilp``
LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.2.0>`__.
LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__.

``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__.
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2 changes: 1 addition & 1 deletion llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -174,7 +174,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {

{"zfbfmin", RISCVExtensionVersion{0, 8}},

{"zicfilp", RISCVExtensionVersion{0, 2}},
{"zicfilp", RISCVExtensionVersion{0, 4}},
{"zicond", RISCVExtensionVersion{1, 0}},

{"ztso", RISCVExtensionVersion{0, 1}},
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -271,7 +271,7 @@
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"

; RV64M: .attribute 5, "rv64i2p1_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
Expand Down Expand Up @@ -360,7 +360,7 @@
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p2"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"

define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
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4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -309,5 +309,5 @@
.attribute arch, "rv32i_xcvbi"
# CHECK: attribute 5, "rv32i2p1_xcvbi1p0"

.attribute arch, "rv32i_zicfilp0p2"
# CHECK: attribute 5, "rv32i2p1_zicfilp0p2"
.attribute arch, "rv32i_zicfilp0p4"
# CHECK: attribute 5, "rv32i2p1_zicfilp0p4"
2 changes: 1 addition & 1 deletion llvm/unittests/Support/RISCVISAInfoTest.cpp
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Expand Up @@ -736,7 +736,7 @@ R"(All available -march extensions for RISC-V
xventanacondops 1.0

Experimental extensions
zicfilp 0.2 This is a long dummy description
zicfilp 0.4 This is a long dummy description
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What does "This is a long dummy description" mean here?

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It's added by #66715. I guess it is means that we don't check the description.

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Ok thanks

zicond 1.0
zacas 1.0
zfbfmin 0.8
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