Skip to content

[AArch64] Add PMOV aliases with implicit portion index #76056

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jan 3, 2024
Merged

[AArch64] Add PMOV aliases with implicit portion index #76056

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
12 changes: 12 additions & 0 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10082,6 +10082,12 @@ multiclass sve2p1_vector_to_pred<string mnemonic, SDPatternOperator Op_lane, SDP

def : InstAlias<mnemonic # "\t$Pd, $Zn",
(!cast<Instruction>(NAME # _B) PPR8:$Pd, ZPRAny:$Zn, 0), 1>;
def : InstAlias<mnemonic # "\t$Pd, $Zn",
(!cast<Instruction>(NAME # _H) PPR16:$Pd, ZPRAny:$Zn, 0), 0>;
def : InstAlias<mnemonic # "\t$Pd, $Zn",
(!cast<Instruction>(NAME # _S) PPR32:$Pd, ZPRAny:$Zn, 0), 0>;
def : InstAlias<mnemonic # "\t$Pd, $Zn",
(!cast<Instruction>(NAME # _D) PPR64:$Pd, ZPRAny:$Zn, 0), 0>;

// any_lane
def : Pat<(nxv16i1 (Op_lane (nxv16i8 ZPRAny:$Zn), (i32 timm32_0_0:$Idx))),
Expand Down Expand Up @@ -10143,6 +10149,12 @@ multiclass sve2p1_pred_to_vector<string mnemonic, SDPatternOperator MergeOp,

def : InstAlias<mnemonic # "\t$Zd, $Pn",
(!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>;
def : InstAlias<mnemonic # "\t$Zd, $Pn",
(!cast<Instruction>(NAME # _H) ZPRAny:$Zd, 0, PPR16:$Pn), 0>;
def : InstAlias<mnemonic # "\t$Zd, $Pn",
(!cast<Instruction>(NAME # _S) ZPRAny:$Zd, 0, PPR32:$Pn), 0>;
def : InstAlias<mnemonic # "\t$Zd, $Pn",
(!cast<Instruction>(NAME # _D) ZPRAny:$Zd, 0, PPR64:$Pn), 0>;

// Merge
def : Pat<(nxv8i16 (MergeOp (nxv8i16 ZPRAny:$Zd), (nxv8i1 PPR16:$Pn), (i32 timm32_1_1:$Idx))),
Expand Down
36 changes: 36 additions & 0 deletions llvm/test/MC/AArch64/SVE2p1/pmov.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,12 @@ pmov p0.h, z0[0] // 00000101-00101100-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 052c3800 <unknown>

pmov p0.h, z0 // 00000101-00101100-00111000-00000000
// CHECK-INST: pmov p0.h, z0[0]
// CHECK-ENCODING: [0x00,0x38,0x2c,0x05]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 052c3800 <unknown>

pmov p5.h, z10[0] // 00000101-00101100-00111001-01000101
// CHECK-INST: pmov p5.h, z10[0]
// CHECK-ENCODING: [0x45,0x39,0x2c,0x05]
Expand All @@ -44,6 +50,12 @@ pmov p0.s, z0[0] // 00000101-01101000-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05683800 <unknown>

pmov p0.s, z0 // 00000101-01101000-00111000-00000000
// CHECK-INST: pmov p0.s, z0[0]
// CHECK-ENCODING: [0x00,0x38,0x68,0x05]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05683800 <unknown>

pmov p5.s, z10[2] // 00000101-01101100-00111001-01000101
// CHECK-INST: pmov p5.s, z10[2]
// CHECK-ENCODING: [0x45,0x39,0x6c,0x05]
Expand All @@ -68,6 +80,12 @@ pmov p0.d, z0[0] // 00000101-10101000-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05a83800 <unknown>

pmov p0.d, z0 // 00000101-10101000-00111000-00000000
// CHECK-INST: pmov p0.d, z0[0]
// CHECK-ENCODING: [0x00,0x38,0xa8,0x05]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05a83800 <unknown>

pmov p5.d, z10[6] // 00000101-11101100-00111001-01000101
// CHECK-INST: pmov p5.d, z10[6]
// CHECK-ENCODING: [0x45,0x39,0xec,0x05]
Expand Down Expand Up @@ -122,6 +140,12 @@ pmov z0[0], p0.h // 00000101-00101101-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 052d3800 <unknown>

pmov z0, p0.h // 00000101-00101101-00111000-00000000
// CHECK-INST: pmov z0[0], p0.h
// CHECK-ENCODING: [0x00,0x38,0x2d,0x05]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 052d3800 <unknown>

pmov z21[0], p10.h // 00000101-00101101-00111001-01010101
// CHECK-INST: pmov z21[0], p10.h
// CHECK-ENCODING: [0x55,0x39,0x2d,0x05]
Expand All @@ -147,6 +171,12 @@ pmov z0[0], p0.s // 00000101-01101001-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05693800 <unknown>

pmov z0, p0.s // 00000101-01101001-00111000-00000000
// CHECK-INST: pmov z0[0], p0.s
// CHECK-ENCODING: [0x00,0x38,0x69,0x05]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05693800 <unknown>

pmov z21[2], p10.s // 00000101-01101101-00111001-01010101
// CHECK-INST: pmov z21[2], p10.s
// CHECK-ENCODING: [0x55,0x39,0x6d,0x05]
Expand All @@ -171,6 +201,12 @@ pmov z0[0], p0.d // 00000101-10101001-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05a93800 <unknown>

pmov z0, p0.d // 00000101-10101001-00111000-00000000
// CHECK-INST: pmov z0[0], p0.d
// CHECK-ENCODING: [0x00,0x38,0xa9,0x05]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05a93800 <unknown>

pmov z21[6], p10.d // 00000101-11101101-00111001-01010101
// CHECK-INST: pmov z21[6], p10.d
// CHECK-ENCODING: [0x55,0x39,0xed,0x05]
Expand Down