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Reland [RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg #81124

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Reland [RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg #81124

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05077e9
[RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl
asb Feb 8, 2024
20f5958
Reland [RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg
asb Feb 8, 2024
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33 changes: 33 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1579,6 +1579,12 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
break;
case RISCV::ADD:
if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0)
return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
if (MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0)
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
break;
case RISCV::ADDI:
// Operand 1 can be a frameindex but callers expect registers
if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
Expand Down Expand Up @@ -2556,6 +2562,33 @@ std::optional<RegImmPair> RISCVInstrInfo::isAddImmediate(const MachineInstr &MI,
return std::nullopt;
}

bool RISCVInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
const Register Reg,
int64_t &ImmVal) const {
// Handle moves of X0.
if (auto DestSrc = isCopyInstr(MI)) {
if (DestSrc->Source->getReg() != RISCV::X0)
return false;
const Register DstReg = DestSrc->Destination->getReg();
if (DstReg != Reg)
return false;
ImmVal = 0;
return true;
}

if (!(MI.getOpcode() == RISCV::ADDI || MI.getOpcode() == RISCV::ADDIW ||
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Can we reuse TII's ::isAddImmediate here? It only covers the ADDI case, but we could land that, and then extend it to cover the other cases.

MI.getOpcode() == RISCV::ORI))
return false;
if (MI.getOperand(0).getReg() != Reg)
return false;
if (!MI.getOperand(1).isReg() || MI.getOperand(1).getReg() != RISCV::X0)
return false;
if (!MI.getOperand(2).isImm())
return false;
ImmVal = MI.getOperand(2).getImm();
return true;
}

// MIR printer helper function to annotate Operands with a comment.
std::string RISCVInstrInfo::createMIROperandComment(
const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -212,6 +212,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
Register Reg) const override;

bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
int64_t &ImmVal) const override;

bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
unsigned &SrcOpIdx2) const override;
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
Expand Down
56 changes: 53 additions & 3 deletions llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
EXPECT_EQ(MI4Res->Destination->getReg(), RISCV::F1_D);
EXPECT_EQ(MI4Res->Source->getReg(), RISCV::F2_D);

// ADD. TODO: Should return true for add reg, x0 and add x0, reg.
// ADD.
MachineInstr *MI5 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
.addReg(RISCV::X2)
.addReg(RISCV::X3)
Expand All @@ -147,14 +147,64 @@ TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
.addReg(RISCV::X2)
.getInstr();
auto MI6Res = TII->isCopyInstrImpl(*MI6);
EXPECT_FALSE(MI6Res.has_value());
ASSERT_TRUE(MI6Res.has_value());
EXPECT_EQ(MI6Res->Destination->getReg(), RISCV::X1);
EXPECT_EQ(MI6Res->Source->getReg(), RISCV::X2);

MachineInstr *MI7 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
.addReg(RISCV::X2)
.addReg(RISCV::X0)
.getInstr();
auto MI7Res = TII->isCopyInstrImpl(*MI7);
EXPECT_FALSE(MI7Res.has_value());
ASSERT_TRUE(MI7Res.has_value());
EXPECT_EQ(MI7Res->Destination->getReg(), RISCV::X1);
EXPECT_EQ(MI7Res->Source->getReg(), RISCV::X2);
}

TEST_P(RISCVInstrInfoTest, GetConstValDefinedInReg) {
const RISCVInstrInfo *TII = ST->getInstrInfo();
DebugLoc DL;
int64_t ImmVal;

auto *MI1 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
.addReg(RISCV::X2)
.addReg(RISCV::X3)
.getInstr();
EXPECT_FALSE(TII->getConstValDefinedInReg(*MI1, RISCV::X1, ImmVal));

auto *MI2 = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X1)
.addReg(RISCV::X0)
.addImm(-128)
.getInstr();
EXPECT_FALSE(TII->getConstValDefinedInReg(*MI2, RISCV::X0, ImmVal));
ASSERT_TRUE(TII->getConstValDefinedInReg(*MI2, RISCV::X1, ImmVal));
EXPECT_EQ(ImmVal, -128);

auto *MI3 = BuildMI(*MF, DL, TII->get(RISCV::ORI), RISCV::X2)
.addReg(RISCV::X0)
.addImm(1024)
.getInstr();
EXPECT_FALSE(TII->getConstValDefinedInReg(*MI3, RISCV::X0, ImmVal));
ASSERT_TRUE(TII->getConstValDefinedInReg(*MI3, RISCV::X2, ImmVal));
EXPECT_EQ(ImmVal, 1024);

if (ST->is64Bit()) {
auto *MI4 = BuildMI(*MF, DL, TII->get(RISCV::ADDIW), RISCV::X2)
.addReg(RISCV::X0)
.addImm(512)
.getInstr();
EXPECT_FALSE(TII->getConstValDefinedInReg(*MI4, RISCV::X0, ImmVal));
ASSERT_TRUE(TII->getConstValDefinedInReg(*MI4, RISCV::X2, ImmVal));
EXPECT_EQ(ImmVal, 512);
}

auto *MI5 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
.addReg(RISCV::X0)
.addReg(RISCV::X0)
.getInstr();
EXPECT_FALSE(TII->getConstValDefinedInReg(*MI5, RISCV::X0, ImmVal));
ASSERT_TRUE(TII->getConstValDefinedInReg(*MI5, RISCV::X1, ImmVal));
EXPECT_EQ(ImmVal, 0);
}

TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
Expand Down