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[AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. #82233

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Merged
merged 1 commit into from
Feb 20, 2024
+36 −61
Merged

[AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. #82233

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13 changes: 1 addition & 12 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -457,8 +457,6 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes_,
uint64_t Address,
raw_ostream &CS) const {
bool IsSDWA = false;

unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
Bytes = Bytes_.slice(0, MaxInstBytesNum);

Expand Down Expand Up @@ -572,15 +570,6 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
break;
}

Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS);
if (Res) { IsSDWA = true; break; }

Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS);
if (Res) { IsSDWA = true; break; }

Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS);
if (Res) { IsSDWA = true; break; }

if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) {
Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS);
if (Res)
Expand Down Expand Up @@ -771,7 +760,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP))
Res = convertVINTERPInst(MI);

if (Res && IsSDWA)
if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA))
Res = convertSDWAInst(MI);

int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
Expand Down
8 changes: 2 additions & 6 deletions llvm/lib/Target/AMDGPU/VOP1Instructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -985,15 +985,11 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
def _sdwa_gfx10 :
VOP_SDWA10_Real<!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
VOP1_SDWA9Ae<op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
let DecoderNamespace = "SDWA10";
}
VOP1_SDWA9Ae<op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
}
multiclass VOP1_Real_dpp_gfx10<bits<9> op> {
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
def _dpp_gfx10 : VOP1_DPP16<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10> {
let DecoderNamespace = "SDWA10";
}
def _dpp_gfx10 : VOP1_DPP16<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10>;
}
multiclass VOP1_Real_dpp8_gfx10<bits<9> op> {
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
Expand Down
70 changes: 30 additions & 40 deletions llvm/lib/Target/AMDGPU/VOP2Instructions.td
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Expand Up @@ -1740,15 +1740,11 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
def _sdwa_gfx10 :
VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
let DecoderNamespace = "SDWA10";
}
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
}
multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10> {
let DecoderNamespace = "SDWA10";
}
def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10>;
}
multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
Expand Down Expand Up @@ -1777,35 +1773,33 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
let AsmString = asmName # ps.AsmOperands;
}
}
let DecoderNamespace = "SDWA10" in {
multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
string asmName> {
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then
def _sdwa_gfx10 :
VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
let AsmString = asmName # ps.AsmOperands;
}
}
multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
string asmName> {
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10> {
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
let AsmString = asmName # ps.Pfl.AsmDPP16;
multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
string asmName> {
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then
def _sdwa_gfx10 :
VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
let AsmString = asmName # ps.AsmOperands;
}
}
multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
string asmName> {
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10> {
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
let AsmString = asmName # ps.Pfl.AsmDPP16;
}
multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
string asmName> {
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
let AsmString = asmName # ps.Pfl.AsmDPP8;
let DecoderNamespace = "DPP8";
}
}
multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
string asmName> {
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
let AsmString = asmName # ps.Pfl.AsmDPP8;
let DecoderNamespace = "DPP8";
}
} // End DecoderNamespace = "SDWA10"
}

//===------------------------------ VOP2be ------------------------------===//
multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
Expand All @@ -1832,7 +1826,6 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
let DecoderNamespace = "SDWA10";
}
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then
def _sdwa_w32_gfx10 :
Expand All @@ -1841,17 +1834,15 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
let isAsmParserOnly = 1;
let DecoderNamespace = "SDWA10";
let WaveSizePredicate = isWave32;
}
}
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then
def _sdwa_w64_gfx10 :
Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
let AsmString = asmName # Ps.AsmOperands;
let isAsmParserOnly = 1;
let DecoderNamespace = "SDWA10";
let WaveSizePredicate = isWave64;
}
}
Expand All @@ -1861,7 +1852,6 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10, asmName> {
string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
let AsmString = asmName # !subst(", vcc", "", AsmDPP);
let DecoderNamespace = "SDWA10";
}
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
def _dpp_w32_gfx10 :
Expand Down Expand Up @@ -2305,7 +2295,7 @@ multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
let AsmString = AsmName # ps.AsmOperands;
let DecoderNamespace = "SDWA9";
let DecoderNamespace = "GFX9";
}
}

Expand All @@ -2329,7 +2319,7 @@ multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
def _dpp_gfx9 :
VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
let DecoderNamespace = "SDWA9";
let DecoderNamespace = "GFX9";
}
}

Expand Down Expand Up @@ -2489,7 +2479,7 @@ let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in {
def _dpp_gfx90a :
VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>,
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
let DecoderNamespace = "SDWA9";
let DecoderNamespace = "GFX9";
}
}
} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/VOPInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -616,7 +616,7 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
let AssemblerPredicate = HasSDWA;
let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
AMDGPUAsmVariants.Disable);
let DecoderNamespace = "SDWA";
let DecoderNamespace = "GFX8";

VOPProfile Pfl = P;
}
Expand Down Expand Up @@ -672,7 +672,7 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
let AssemblerPredicate = HasSDWA9;
let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9,
AMDGPUAsmVariants.Disable);
let DecoderNamespace = "SDWA9";
let DecoderNamespace = "GFX9";

// Copy relevant pseudo op flags
let AsmMatchConverter = ps.AsmMatchConverter;
Expand All @@ -693,7 +693,7 @@ class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> {
let SubtargetPredicate = HasSDWA10;
let AssemblerPredicate = HasSDWA10;
let DecoderNamespace = "SDWA10";
let DecoderNamespace = "GFX10";
}

class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> :
Expand Down