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[AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for add/sub. #88413

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Merged
merged 3 commits into from
Apr 19, 2024
Merged

[AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for add/sub. #88413

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4635801
[AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for add/sub.
Apr 11, 2024
ccab06a
Resolved remarks.
Apr 15, 2024
cbc085d
Removed isConstantSplatVector duplicates.
Apr 17, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17927,11 +17927,11 @@ static SDValue tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
} else
continue;

if (!ISD::isBuildVectorAllZeros(Sub.getOperand(0).getNode()))
if (!ISD::isConstantSplatVectorAllZeros(Sub.getOperand(0).getNode()))
continue;

// Constant ones is always righthand operand of the Add.
if (!ISD::isBuildVectorAllOnes(Add.getOperand(1).getNode()))
if (!ISD::isConstantSplatVectorAllOnes(Add.getOperand(1).getNode()))
continue;

if (Sub.getOperand(1) != Add.getOperand(0))
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15 changes: 15 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2-bsl.ll
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Expand Up @@ -13,6 +13,21 @@ define <vscale x 4 x i32> @bsl(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
ret <vscale x 4 x i32> %c
}

define <vscale x 4 x i32> @bsl_add_sub(<vscale x 4 x i32> %pre_cond, <vscale x 4 x i32> %left, <vscale x 4 x i32> %right) #0 {
; CHECK-LABEL: bsl_add_sub:
; CHECK: // %bb.0:
; CHECK-NEXT: subr z0.s, z0.s, #0 // =0x0
; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ret
%neg_cond = sub <vscale x 4 x i32> zeroinitializer, %pre_cond
%min_cond = add <vscale x 4 x i32> %pre_cond, splat(i32 -1)
%left_bits_0 = and <vscale x 4 x i32> %neg_cond, %left
%right_bits_0 = and <vscale x 4 x i32> %min_cond, %right
%bsl0000 = or <vscale x 4 x i32> %right_bits_0, %left_bits_0
ret <vscale x 4 x i32> %bsl0000
}

; we are not expecting bsl instruction here. the constants do not match to fold to bsl.
define <vscale x 4 x i32> @no_bsl_fold(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: no_bsl_fold:
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