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[AMDGPU] Fix mode register pass for constrained FP operations #90085

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Merged
merged 5 commits into from
May 3, 2024
Merged

[AMDGPU] Fix mode register pass for constrained FP operations #90085

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341ac99
[AMDGPU] Fix mode register pass for constrained FP operations
abhigargrepo Apr 25, 2024
91bc013
Merge branch 'main' into fixBug-siMode
abhigargrepo Apr 25, 2024
3f5392d
[AMDGPU] Fix mode register pass for constrained FP operations
abhigargrepo Apr 25, 2024
74ca2cf
Merge branch 'main' into fixBug-siMode
abhigargrepo Apr 30, 2024
a7f5bca
[AMDGPU] Fix mode register pass for constrained FP operations
abhigargrepo Apr 30, 2024
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8 changes: 8 additions & 0 deletions llvm/lib/Target/AMDGPU/SIModeRegister.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -430,6 +430,14 @@ void SIModeRegister::processBlockPhase3(MachineBasicBlock &MBB,
}

bool SIModeRegister::runOnMachineFunction(MachineFunction &MF) {
// Constrained FP intrinsics are used to support non-default rounding modes.
// strictfp attribute is required to mark functions with strict FP semantics
// having constrained FP intrinsics. This pass fixes up operations that uses
// a non-default rounding mode for non-strictfp functions. But it should not
// assume or modify any default rounding modes in case of strictfp functions.
const Function &F = MF.getFunction();
if (F.hasFnAttribute(llvm::Attribute::StrictFP))
return Changed;
BlockInfo.resize(MF.getNumBlockIDs());
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const SIInstrInfo *TII = ST.getInstrInfo();
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4 changes: 0 additions & 4 deletions llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
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Expand Up @@ -9,8 +9,6 @@ define double @ignoreStrictfp(double noundef %a, double noundef %b) #0 {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
; GCN-NEXT: s_nop 1
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GCN-NEXT: s_setpc_b64 s[30:31]
tail call void @llvm.amdgcn.s.setreg(i32 2177, i32 1)
Expand All @@ -24,8 +22,6 @@ define double @set_fpenv(double noundef %a, double noundef %b) #0 {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 23), 4
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 0, 5), 0
; GCN-NEXT: s_nop 0
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
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