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[AMDGPU] Check MIR after SIMemoryLegalizer instead of final ISA #90601

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[AMDGPU] Check MIR after SIMemoryLegalizer instead of final ISA #90601

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5,148 changes: 2,824 additions & 2,324 deletions llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
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31,243 changes: 16,777 additions & 14,466 deletions llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
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95 changes: 48 additions & 47 deletions llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
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Original file line number Diff line number Diff line change
@@ -1,38 +1,37 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12,GFX12-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX12,GFX12-CU %s
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12,GFX12-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=si-memory-legalizer -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX12,GFX12-CU %s

define amdgpu_kernel void @flat_last_use_load_0(ptr %in, ptr %out) {
; GFX12-LABEL: flat_last_use_load_0:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: flat_load_b32 v2, v[0:1] th:TH_LOAD_LU
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: flat_store_b32 v[0:1], v2
; GFX12-NEXT: s_endpgm
; GFX12-LABEL: name: flat_last_use_load_0
; GFX12: bb.0.entry:
; GFX12-NEXT: liveins: $sgpr0_sgpr1
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s128) from %ir.in.kernarg.offset1, addrspace 4)
; GFX12-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $sgpr0, killed $sgpr1, implicit $exec, implicit $exec, implicit $exec, implicit $exec, implicit $exec
; GFX12-NEXT: renamable $vgpr2 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 3, implicit $exec, implicit $flat_scr :: ("amdgpu-last-use" load (s32) from %ir.1)
; GFX12-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $sgpr2, killed $sgpr3, implicit $exec, implicit $exec, implicit $exec, implicit $exec, implicit $exec
; GFX12-NEXT: FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.2)
; GFX12-NEXT: S_ENDPGM 0
entry:
%val = load i32, ptr %in, align 4, !amdgpu.last.use !{}
store i32 %val, ptr %out
ret void
}

define amdgpu_kernel void @flat_last_use_load_1(ptr %in, ptr %out) {
; GFX12-LABEL: flat_last_use_load_1:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_u32 v0, s0, s0, v0
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
; GFX12-NEXT: flat_load_b32 v2, v[0:1] th:TH_LOAD_LU
; GFX12-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: flat_store_b32 v[0:1], v2
; GFX12-NEXT: s_endpgm
; GFX12-LABEL: name: flat_last_use_load_1
; GFX12: bb.0.entry:
; GFX12-NEXT: liveins: $vgpr0, $sgpr0_sgpr1
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s128) from %ir.in.kernarg.offset1, addrspace 4)
; GFX12-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec
; GFX12-NEXT: renamable $vgpr0, renamable $sgpr0 = V_ADD_CO_U32_e64 killed $sgpr0, killed $vgpr0, 0, implicit $exec
; GFX12-NEXT: renamable $vgpr1, dead $sgpr_null = V_ADDC_U32_e64 killed $sgpr1, 0, killed $sgpr0, 0, implicit $exec
; GFX12-NEXT: renamable $vgpr2 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 3, implicit $exec, implicit $flat_scr :: ("amdgpu-last-use" load (s32) from %ir.val.gep)
; GFX12-NEXT: $vgpr1, $vgpr0 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $sgpr3, killed $sgpr2, implicit $exec, implicit $exec, implicit $exec, implicit $exec, implicit $exec
; GFX12-NEXT: FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.2)
; GFX12-NEXT: S_ENDPGM 0
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, ptr %in, i32 %tid
Expand All @@ -42,34 +41,36 @@ entry:
}

define amdgpu_kernel void @flat_last_use_and_volatile_load(ptr %in, ptr %out) {
; GFX12-LABEL: flat_last_use_and_volatile_load:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: flat_load_b32 v2, v[0:1] th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: flat_store_b32 v[0:1], v2
; GFX12-NEXT: s_endpgm
; GFX12-LABEL: name: flat_last_use_and_volatile_load
; GFX12: bb.0.entry:
; GFX12-NEXT: liveins: $sgpr0_sgpr1
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s128) from %ir.in.kernarg.offset1, addrspace 4)
; GFX12-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $sgpr0, killed $sgpr1, implicit $exec, implicit $exec, implicit $exec, implicit $exec, implicit $exec
; GFX12-NEXT: renamable $vgpr2 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 27, implicit $exec, implicit $flat_scr :: (volatile "amdgpu-last-use" load (s32) from %ir.1)
; GFX12-NEXT: S_WAIT_BVHCNT_soft 0
; GFX12-NEXT: S_WAIT_SAMPLECNT_soft 0
; GFX12-NEXT: S_WAIT_LOADCNT_soft 0
; GFX12-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $sgpr2, killed $sgpr3, implicit $exec, implicit $exec, implicit $exec, implicit $exec, implicit $exec
; GFX12-NEXT: FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.2)
; GFX12-NEXT: S_ENDPGM 0
entry:
%val = load volatile i32, ptr %in, align 4, !amdgpu.last.use !{}
store i32 %val, ptr %out
ret void
}

define amdgpu_kernel void @flat_last_use_and_nontemporal_load(ptr %in, ptr %out) {
; GFX12-LABEL: flat_last_use_and_nontemporal_load:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: flat_load_b32 v2, v[0:1] th:TH_LOAD_LU
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: flat_store_b32 v[0:1], v2
; GFX12-NEXT: s_endpgm
; GFX12-LABEL: name: flat_last_use_and_nontemporal_load
; GFX12: bb.0.entry:
; GFX12-NEXT: liveins: $sgpr0_sgpr1
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s128) from %ir.in.kernarg.offset1, addrspace 4)
; GFX12-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $sgpr0, killed $sgpr1, implicit $exec, implicit $exec, implicit $exec, implicit $exec, implicit $exec
; GFX12-NEXT: renamable $vgpr2 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 3, implicit $exec, implicit $flat_scr :: (non-temporal "amdgpu-last-use" load (s32) from %ir.1)
; GFX12-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $sgpr2, killed $sgpr3, implicit $exec, implicit $exec, implicit $exec, implicit $exec, implicit $exec
; GFX12-NEXT: FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.2)
; GFX12-NEXT: S_ENDPGM 0
entry:
%val = load i32, ptr %in, align 4, !amdgpu.last.use !{}, !nontemporal !0
store i32 %val, ptr %out
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