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[AMDGPU] Change getLdStRegisterOperand to !cond for better diagnostic #95475

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Merged
merged 1 commit into from
Jun 14, 2024
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[AMDGPU] Change getLdStRegisterOperand to !cond for better diagnostic #95475

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10 changes: 4 additions & 6 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -399,12 +399,10 @@ class MUBUF_Invalidate <string opName, SDPatternOperator node = null_frag> :

class getLdStVDataRegisterOperand<RegisterClass RC, bit isTFE> {
RegisterOperand tfeVDataOp =
!if(!eq(RC.Size, 32), AVLdSt_64,
!if(!eq(RC.Size, 64), AVLdSt_96,
!if(!eq(RC.Size, 96), AVLdSt_128,
!if(!eq(RC.Size, 128), AVLdSt_160,
RegisterOperand<VReg_1> // Invalid register.
))));
!cond(!eq(RC.Size, 32) : AVLdSt_64,
!eq(RC.Size, 64) : AVLdSt_96,
!eq(RC.Size, 96) : AVLdSt_128,
!eq(RC.Size, 128) : AVLdSt_160);

RegisterOperand ret = !if(isTFE, tfeVDataOp, getLdStRegisterOperand<RC>.ret);
}
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12 changes: 5 additions & 7 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -2242,13 +2242,11 @@ class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
// Return an AGPR+VGPR operand class for the given VGPR register class.
class getLdStRegisterOperand<RegisterClass RC> {
RegisterOperand ret =
!if(!eq(RC.Size, 32), AVLdSt_32,
!if(!eq(RC.Size, 64), AVLdSt_64,
!if(!eq(RC.Size, 96), AVLdSt_96,
!if(!eq(RC.Size, 128), AVLdSt_128,
!if(!eq(RC.Size, 160), AVLdSt_160,
RegisterOperand<VReg_1> // invalid register
)))));
!cond(!eq(RC.Size, 32) : AVLdSt_32,
!eq(RC.Size, 64) : AVLdSt_64,
!eq(RC.Size, 96) : AVLdSt_96,
!eq(RC.Size, 128) : AVLdSt_128,
!eq(RC.Size, 160) : AVLdSt_160);
}

class getHasVOP3DPP <ValueType DstVT = i32, ValueType Src0VT = i32,
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