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[DAG] ComputeNumSignBits - subo_carry(x,x,c) -> bitwidth 'allsignbits' #99935

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Merged
merged 1 commit into from
Jul 23, 2024
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[DAG] ComputeNumSignBits - subo_carry(x,x,c) -> bitwidth 'allsignbits' #99935

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8 changes: 6 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4705,14 +4705,18 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
return 1; // Early out.
Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
return std::min(Tmp, Tmp2);
case ISD::SSUBO_CARRY:
case ISD::USUBO_CARRY:
// sub_carry(x,x,c) -> 0/-1 (sext carry)
if (Op.getResNo() == 0 && Op.getOperand(0) == Op.getOperand(1))
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Do we need to check getBooleanContents here?

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Nevermind, this is result 0.

return VTBits;
[[fallthrough]];
case ISD::SADDO:
case ISD::UADDO:
case ISD::SADDO_CARRY:
case ISD::UADDO_CARRY:
case ISD::SSUBO:
case ISD::USUBO:
case ISD::SSUBO_CARRY:
case ISD::USUBO_CARRY:
case ISD::SMULO:
case ISD::UMULO:
if (Op.getResNo() != 1)
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2 changes: 0 additions & 2 deletions llvm/test/CodeGen/AArch64/neon-abd.ll
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Expand Up @@ -332,8 +332,6 @@ define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) #0 {
; CHECK-NEXT: ngc x9, xzr
; CHECK-NEXT: subs x10, x10, x11
; CHECK-NEXT: ngc x11, xzr
; CHECK-NEXT: asr x9, x9, #63
; CHECK-NEXT: asr x11, x11, #63
; CHECK-NEXT: eor x8, x8, x9
; CHECK-NEXT: eor x10, x10, x11
; CHECK-NEXT: sub x8, x8, x9
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/ARM/neon_vabd.ll
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Expand Up @@ -340,20 +340,20 @@ define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: sbcs r2, r3, r12
; CHECK-NEXT: sbcs r3, r1, #0
; CHECK-NEXT: sbc r3, r1, #0
; CHECK-NEXT: eor r0, r0, r3, asr #31
; CHECK-NEXT: eor r2, r2, r3, asr #31
; CHECK-NEXT: subs r0, r0, r3, asr #31
; CHECK-NEXT: sbc r2, r2, r3, asr #31
; CHECK-NEXT: eor r0, r0, r3
; CHECK-NEXT: eor r2, r2, r3
; CHECK-NEXT: subs r0, r0, r3
; CHECK-NEXT: sbc r2, r2, r3
; CHECK-NEXT: subs r3, r4, lr
; CHECK-NEXT: sbcs r6, r5, r6
; CHECK-NEXT: vmov.32 d1[0], r0
; CHECK-NEXT: sbcs r5, r1, #0
; CHECK-NEXT: sbc r1, r1, #0
; CHECK-NEXT: eor r3, r3, r1, asr #31
; CHECK-NEXT: subs r0, r3, r1, asr #31
; CHECK-NEXT: eor r3, r3, r1
; CHECK-NEXT: subs r0, r3, r1
; CHECK-NEXT: vmov.32 d0[0], r0
; CHECK-NEXT: eor r0, r6, r1, asr #31
; CHECK-NEXT: sbc r0, r0, r1, asr #31
; CHECK-NEXT: eor r0, r6, r1
; CHECK-NEXT: sbc r0, r0, r1
; CHECK-NEXT: vmov.32 d1[1], r2
; CHECK-NEXT: vmov.32 d0[1], r0
; CHECK-NEXT: pop {r4, r5, r6, pc}
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2 changes: 0 additions & 2 deletions llvm/test/CodeGen/X86/abdu.ll
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Expand Up @@ -289,7 +289,6 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; X86-NEXT: movl $0, %esi
; X86-NEXT: sbbl %esi, %esi
; X86-NEXT: sbbl %ecx, %ecx
; X86-NEXT: sarl $31, %ecx
; X86-NEXT: xorl %ecx, %edx
; X86-NEXT: xorl %ecx, %eax
; X86-NEXT: subl %ecx, %eax
Expand Down Expand Up @@ -325,7 +324,6 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; X86-NEXT: movl $0, %esi
; X86-NEXT: sbbl %esi, %esi
; X86-NEXT: sbbl %ecx, %ecx
; X86-NEXT: sarl $31, %ecx
; X86-NEXT: xorl %ecx, %edx
; X86-NEXT: xorl %ecx, %eax
; X86-NEXT: subl %ecx, %eax
Expand Down
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