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[RISCV] Use VP strided load in concat_vectors combine
After llvm#98112 and llvm#98111 this should be the last use of riscv_masked_strided_load. The diff is due to vp_load not having the same generic combine for bitcasts where `(conv (load x)) -> (load (conv*)x)`. I don't think this makes much of a difference on RVV, and it doesn't seem to affect other patterns.
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2 files changed

+14
-19
lines changed

2 files changed

+14
-19
lines changed

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -16205,18 +16205,10 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
1620516205
if (MustNegateStride)
1620616206
Stride = DAG.getNegative(Stride, DL, Stride.getValueType());
1620716207

16208-
SDVTList VTs = DAG.getVTList({WideVecVT, MVT::Other});
16209-
SDValue IntID =
16210-
DAG.getTargetConstant(Intrinsic::riscv_masked_strided_load, DL,
16211-
Subtarget.getXLenVT());
16212-
1621316208
SDValue AllOneMask =
1621416209
DAG.getSplat(WideVecVT.changeVectorElementType(MVT::i1), DL,
1621516210
DAG.getConstant(1, DL, MVT::i1));
1621616211

16217-
SDValue Ops[] = {BaseLd->getChain(), IntID, DAG.getUNDEF(WideVecVT),
16218-
BaseLd->getBasePtr(), Stride, AllOneMask};
16219-
1622016212
uint64_t MemSize;
1622116213
if (auto *ConstStride = dyn_cast<ConstantSDNode>(Stride);
1622216214
ConstStride && ConstStride->getSExtValue() >= 0)
@@ -16232,8 +16224,11 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
1623216224
BaseLd->getPointerInfo(), BaseLd->getMemOperand()->getFlags(), MemSize,
1623316225
Align);
1623416226

16235-
SDValue StridedLoad = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs,
16236-
Ops, WideVecVT, MMO);
16227+
SDValue StridedLoad = DAG.getStridedLoadVP(
16228+
WideVecVT, DL, BaseLd->getChain(), BaseLd->getBasePtr(), Stride,
16229+
AllOneMask,
16230+
DAG.getConstant(N->getNumOperands(), DL, Subtarget.getXLenVT()), MMO);
16231+
1623716232
for (SDValue Ld : N->ops())
1623816233
DAG.makeEquivalentMemoryOrdering(cast<LoadSDNode>(Ld), StridedLoad);
1623916234

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,9 @@
99
define void @widen_2xv4i16(ptr %x, ptr %z) {
1010
; CHECK-LABEL: widen_2xv4i16:
1111
; CHECK: # %bb.0:
12-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
13-
; CHECK-NEXT: vle16.v v8, (a0)
14-
; CHECK-NEXT: vse16.v v8, (a1)
12+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
13+
; CHECK-NEXT: vle64.v v8, (a0)
14+
; CHECK-NEXT: vse64.v v8, (a1)
1515
; CHECK-NEXT: ret
1616
%a = load <4 x i16>, ptr %x
1717
%b.gep = getelementptr i8, ptr %x, i64 8
@@ -52,9 +52,9 @@ define void @widen_3xv4i16(ptr %x, ptr %z) {
5252
define void @widen_4xv4i16(ptr %x, ptr %z) {
5353
; CHECK-LABEL: widen_4xv4i16:
5454
; CHECK: # %bb.0:
55-
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
56-
; CHECK-NEXT: vle16.v v8, (a0)
57-
; CHECK-NEXT: vse16.v v8, (a1)
55+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
56+
; CHECK-NEXT: vle64.v v8, (a0)
57+
; CHECK-NEXT: vse64.v v8, (a1)
5858
; CHECK-NEXT: ret
5959
%a = load <4 x i16>, ptr %x
6060
%b.gep = getelementptr i8, ptr %x, i64 8
@@ -90,9 +90,9 @@ define void @widen_4xv4i16_unaligned(ptr %x, ptr %z) {
9090
;
9191
; RV64-MISALIGN-LABEL: widen_4xv4i16_unaligned:
9292
; RV64-MISALIGN: # %bb.0:
93-
; RV64-MISALIGN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
94-
; RV64-MISALIGN-NEXT: vle16.v v8, (a0)
95-
; RV64-MISALIGN-NEXT: vse16.v v8, (a1)
93+
; RV64-MISALIGN-NEXT: vsetivli zero, 4, e64, m2, ta, ma
94+
; RV64-MISALIGN-NEXT: vle64.v v8, (a0)
95+
; RV64-MISALIGN-NEXT: vse64.v v8, (a1)
9696
; RV64-MISALIGN-NEXT: ret
9797
%a = load <4 x i16>, ptr %x, align 1
9898
%b.gep = getelementptr i8, ptr %x, i64 8

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