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[RISCV] Rematerialize vfmv.v.f
This is the same principle as vmv.v.x in llvm#107993, but for floats. Program regalloc.NumSpills regalloc.NumReloads regalloc.NumRemats lhs rhs diff lhs rhs diff lhs rhs diff 519.lbm_r 73.00 73.00 0.0% 75.00 75.00 0.0% 1.00 1.00 0.0% 544.nab_r 753.00 753.00 0.0% 1183.00 1183.00 0.0% 318.00 318.00 0.0% 619.lbm_s 68.00 68.00 0.0% 70.00 70.00 0.0% 1.00 1.00 0.0% 644.nab_s 753.00 753.00 0.0% 1183.00 1183.00 0.0% 318.00 318.00 0.0% 508.namd_r 6598.00 6597.00 -0.0% 15509.00 15503.00 -0.0% 2387.00 2393.00 0.3% 526.blender_r 13105.00 13084.00 -0.2% 26478.00 26443.00 -0.1% 18991.00 18996.00 0.0% 510.parest_r 42740.00 42665.00 -0.2% 82400.00 82309.00 -0.1% 5612.00 5648.00 0.6% 511.povray_r 1937.00 1929.00 -0.4% 3629.00 3620.00 -0.2% 517.00 525.00 1.5% 538.imagick_r 4181.00 4150.00 -0.7% 11342.00 11125.00 -1.9% 3366.00 3366.00 0.0% 638.imagick_s 4181.00 4150.00 -0.7% 11342.00 11125.00 -1.9% 3366.00 3366.00 0.0% Geomean difference -0.2% -0.4% 0.2%
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3 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

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Original file line numberDiff line numberDiff line change
@@ -170,6 +170,7 @@ bool RISCVInstrInfo::isReallyTriviallyReMaterializable(
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const MachineInstr &MI) const {
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switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
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case RISCV::VMV_V_X:
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case RISCV::VFMV_V_F:
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case RISCV::VMV_V_I:
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case RISCV::VID_V:
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if (MI.getOperand(1).isUndef() &&

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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Original file line numberDiff line numberDiff line change
@@ -6558,6 +6558,7 @@ defm PseudoVFMERGE : VPseudoVMRG_FM;
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//===----------------------------------------------------------------------===//
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// 13.16. Vector Floating-Point Move Instruction
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//===----------------------------------------------------------------------===//
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let isReMaterializable = 1 in
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defm PseudoVFMV_V : VPseudoVMV_F;
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//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/remat.ll

Lines changed: 47 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -314,35 +314,53 @@ define void @vmv.v.x_live(ptr %p, i64 %x) {
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}
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define void @vfmv.v.f(ptr %p, double %x) {
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; CHECK-LABEL: vfmv.v.f:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; CHECK-NEXT: vfmv.v.f v8, fa0
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: fsd fa0, 0(a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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; POSTRA-LABEL: vfmv.v.f:
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; POSTRA: # %bb.0:
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; POSTRA-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; POSTRA-NEXT: vfmv.v.f v8, fa0
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: vl8re64.v v16, (a0)
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; POSTRA-NEXT: vl8re64.v v24, (a0)
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; POSTRA-NEXT: vl8re64.v v0, (a0)
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; POSTRA-NEXT: vl8re64.v v8, (a0)
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: vs8r.v v0, (a0)
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; POSTRA-NEXT: vs8r.v v24, (a0)
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; POSTRA-NEXT: vs8r.v v16, (a0)
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; POSTRA-NEXT: vfmv.v.f v8, fa0
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: fsd fa0, 0(a0)
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; POSTRA-NEXT: ret
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;
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; PRERA-LABEL: vfmv.v.f:
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; PRERA: # %bb.0:
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; PRERA-NEXT: addi sp, sp, -16
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; PRERA-NEXT: .cfi_def_cfa_offset 16
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; PRERA-NEXT: csrr a1, vlenb
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; PRERA-NEXT: slli a1, a1, 3
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; PRERA-NEXT: sub sp, sp, a1
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; PRERA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; PRERA-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; PRERA-NEXT: vfmv.v.f v8, fa0
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; PRERA-NEXT: vs8r.v v8, (a0)
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; PRERA-NEXT: vl8re64.v v16, (a0)
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; PRERA-NEXT: addi a1, sp, 16
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; PRERA-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
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; PRERA-NEXT: vl8re64.v v24, (a0)
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; PRERA-NEXT: vl8re64.v v0, (a0)
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; PRERA-NEXT: vl8re64.v v16, (a0)
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; PRERA-NEXT: vs8r.v v16, (a0)
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; PRERA-NEXT: vs8r.v v0, (a0)
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; PRERA-NEXT: vs8r.v v24, (a0)
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; PRERA-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
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; PRERA-NEXT: vs8r.v v16, (a0)
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; PRERA-NEXT: vs8r.v v8, (a0)
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; PRERA-NEXT: fsd fa0, 0(a0)
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; PRERA-NEXT: csrr a0, vlenb
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; PRERA-NEXT: slli a0, a0, 3
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; PRERA-NEXT: add sp, sp, a0
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; PRERA-NEXT: addi sp, sp, 16
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; PRERA-NEXT: ret
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%vfmv.v.f = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64(<vscale x 8 x double> poison, double %x, i64 -1)
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store volatile <vscale x 8 x double> %vfmv.v.f, ptr %p
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