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s-bruce13s-bruce13
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Adding ARM support
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7 files changed

+1504
-2
lines changed

7 files changed

+1504
-2
lines changed

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/CMakeLists.txt

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@@ -17,7 +17,6 @@ target_sources(mbed-imx
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port_api.c
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pwmout_api.c
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rtc_api.c
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sleep.c
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spi_api.c
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watchdog_api.c
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)

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/CMakeLists.txt

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PeripheralPins.c
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pinmap.c
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serial_api.c
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sleep.c
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specific.c
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trng_api.c
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us_ticker.c

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/sleep.c renamed to ‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/sleep.c

File renamed without changes.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt

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add_subdirectory(TARGET_EVK EXCLUDE_FROM_ALL)
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if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
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if(${MBED_TOOLCHAIN} STREQUAL "ARM")
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set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_MIMXRT1176_cm7.S)
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set(LINKER_FILE device/TOOLCHAIN_ARM_STD/MIMXRT1176xxxxx.sct)
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elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
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set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1176_cm7.S)
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set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld)
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endif()

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_ARM_STD/MIMXRT1176xxxxx.sct

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#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
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/*
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** ###################################################################
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** Processors: MIMXRT1176AVM8A_cm7
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** MIMXRT1176CVM8A_cm7
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** MIMXRT1176DVMAA_cm7
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**
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** Compiler: Keil ARM C/C++ Compiler
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** Reference manual: IMXRT1170RM, Rev 0, 12/2020
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** Version: rev. 1.0, 2020-12-29
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** Build: b210202
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**
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** Abstract:
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** Linker file for the Keil ARM C/C++ Compiler
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2021 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: [email protected]
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**
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** ###################################################################
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*/
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#define __ram_vector_table__ 1
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#if (defined(__ram_vector_table__))
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#define __ram_vector_table_size__ 0x00000400
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#else
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#define __ram_vector_table_size__ 0x00000000
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#endif
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x30000400
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#endif
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x1000000
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#endif
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#if !defined(MBED_APP_COMPILE)
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#define m_flash_config_start MBED_APP_START
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#define m_flash_config_size 0x00000C00
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#define m_ivt_start MBED_APP_START + 0x0C00
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#define m_ivt_size 0x00001000
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#define m_interrupts_start MBED_APP_START + 0x1C00
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#define m_interrupts_size 0x00000400
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#define m_text_start MBED_APP_START + 0x2000
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#define m_text_size MBED_APP_SIZE - 0x2000
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#else
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#define m_interrupts_start MBED_APP_START
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#define m_interrupts_size 0x00000400
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#define m_text_start MBED_APP_START + 0x400
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#define m_text_size MBED_APP_SIZE - 0x400
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#endif
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#define m_text2_start 0x00000000
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#define m_text2_size 0x00040000
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#define m_data_start 0x80000000
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#define m_data_size 0x03000000
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#define m_ncache_start 0x83000000
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#define m_ncache_size 0x01000000 - Heap_Size
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#define m_interrupts_ram_start 0x20000000
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#define m_interrupts_ram_size __ram_vector_table_size__
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#define m_data2_start (m_interrupts_ram_start + m_interrupts_ram_size)
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#define m_data2_size (0x00040000 - m_interrupts_ram_size)
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#define m_data3_start 0x202C0000
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#define m_data3_size 0x00080000
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/* Sizes */
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#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
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# if defined(MBED_BOOT_STACK_SIZE)
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# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
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# else
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# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
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# endif
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#endif
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#if (defined(__stack_size__))
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#define Stack_Size __stack_size__
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#else
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#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
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#endif
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#if (defined(__heap_size__))
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#define Heap_Size __heap_size__
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#else
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#define Heap_Size 0x0400
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#endif
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LR_IROM1 MBED_APP_START m_text_start+m_text_size-MBED_APP_START { ; load region size_region
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#if !defined(MBED_APP_COMPILE)
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RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
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* (.boot_hdr.conf, +FIRST)
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}
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RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
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* (.boot_hdr.ivt, +FIRST)
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* (.boot_hdr.boot_data)
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* (.boot_hdr.dcd_data)
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}
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#endif
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VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
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* (RESET,+FIRST)
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}
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ER_IROM1 m_text_start FIXED m_text_size { ; load address = execution address
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* (InRoot$$Sections)
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.ANY (+RO)
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}
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#if (defined(__ram_vector_table__))
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VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
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}
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#else
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VECTOR_RAM m_interrupts_start EMPTY 0 {
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}
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#endif
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RW_m_data m_data_start m_data_size { ; RW data
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.ANY (+RW +ZI)
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*(m_usb_dma_init_data)
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*(m_usb_dma_noninit_data)
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}
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RW_IRAM1 ImageLimit(RW_m_data) {
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_start + m_data_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
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}
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ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
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}
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RW_m_ram_text m_text2_start m_text2_size {
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* (CodeQuickAccess)
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}
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RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
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* (NonCacheable.init)
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* (*NonCacheable)
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}
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}
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