Merge pull request ARMmbed#14567 from OpenNuvoton/nvt_m480_wdt_rst

M487: Resolve WDT reset H/W limit

Author: 0xc0170

targets/TARGET_NUVOTON/TARGET_M480/device/startup_M480.c

@@ -392,10 +392,7 @@ void Reset_Handler_1(void)
 {
     /* Disable register write-protection function */
     SYS_UnlockReg();
-    
-    /* Disable Power-on Reset function */
-    SYS_DISABLE_POR();
-    
+
     /**
      * NOTE 1: Some register accesses require unlock.
      * NOTE 2: Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.

targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c

@@ -18,20 +18,6 @@
 
 #include "analogin_api.h"
 
-void WDT_IRQHandler(void)
-{
-    /* Check WDT interrupt flag */
-    if (WDT_GET_TIMEOUT_INT_FLAG()) {
-        WDT_CLEAR_TIMEOUT_INT_FLAG();
-        WDT_RESET_COUNTER();
-    }
-
-    /* Check WDT wake-up flag */
-    if (WDT_GET_TIMEOUT_WAKEUP_FLAG()) {
-        WDT_CLEAR_TIMEOUT_WAKEUP_FLAG();
-    }
-}
-
 void mbed_sdk_init(void)
 {
     // NOTE: Support singleton semantics to be called from other init functions
@@ -73,7 +59,7 @@ void mbed_sdk_init(void)
 
     /* Set PCLK0/PCLK1 to HCLK/2 */
     CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2); // PCLK divider set 2
-    
+
 #if DEVICE_ANALOGIN
     /* Vref connect to internal */
     SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_0V;
@@ -86,52 +72,22 @@ void mbed_sdk_init(void)
     /* Lock protected registers */
     SYS_LockReg();
 
-    /* Get around h/w issue with reset from power-down mode
-     *
-     * When UART interrupt enabled and WDT reset from power-down mode, in the next
-     * cycle, UART interrupt keeps breaking in and cannot block unless via NVIC. To
-     * get around it, we make up a signal of WDT wake-up from power-down mode in the
-     * start of boot process on detecting WDT reset.
-     */
+    /* Get around h/w limit with WDT reset from PD */
     if (SYS_IS_WDT_RST()) {
-        /* Re-unlock to highlight WDT clock setting is protected */
+        /* Re-unlock protected clock setting */
         SYS_UnlockReg();
 
-        /* Enable IP module clock */
-        CLK_EnableModuleClock(WDT_MODULE);
-
-        /* Select IP clock source */
-        CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0);
+        /* Set up DPD power down mode */
+        CLK->PMUSTS |= CLK_PMUSTS_CLRWK_Msk;
+        CLK->PMUSTS |= CLK_PMUSTS_TMRWK_Msk;
+        CLK_SetPowerDownMode(CLK_PMUCTL_PDMSEL_DPD);
 
-        /* The name of symbol WDT_IRQHandler() is mangled in C++ and cannot
-         * override that in startup file in C. Note the NVIC_SetVector call
-         * cannot be left out when WDT_IRQHandler() is redefined in C++ file.
-         *
-         * NVIC_SetVector(WDT_IRQn, (uint32_t) WDT_IRQHandler);
-         */
-        NVIC_EnableIRQ(WDT_IRQn);
-
-        /* Configure/Enable WDT */
-        WDT->CTL = WDT_TIMEOUT_2POW4 |      // Timeout interval of 2^4 LIRC clocks
-                WDT_CTL_WDTEN_Msk |         // Enable watchdog timer
-                WDT_CTL_INTEN_Msk |         // Enable interrupt
-                WDT_CTL_WKF_Msk |           // Clear wake-up flag
-                WDT_CTL_WKEN_Msk |          // Enable wake-up on timeout
-                WDT_CTL_IF_Msk |            // Clear interrupt flag
-                WDT_CTL_RSTF_Msk |          // Clear reset flag
-                !WDT_CTL_RSTEN_Msk |        // Disable reset
-                WDT_CTL_RSTCNT_Msk;         // Reset up counter
+        CLK_SET_WKTMR_INTERVAL(CLK_PMUCTL_WKTMRIS_256);
+        CLK_ENABLE_WKTMR();
 
         CLK_PowerDown();
 
-        /* Re-unlock for safe */
-        SYS_UnlockReg();
-
-        /* Clear all flags & Disable WDT/INT/WK/RST */
-        WDT->CTL = (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_RSTCNT_Msk);
-
-        NVIC_DisableIRQ(WDT_IRQn);
-
+        /* Lock protected registers */
         SYS_LockReg();
     }
 }

targets/TARGET_NUVOTON/TARGET_M480/reset_reason.c

@@ -39,6 +39,12 @@ reset_reason_t hal_reset_reason_get(void)
     reset_reason_t reset_reason_cast;
     uint32_t reset_reason_count = 0;
 
+    /* Get around h/w limit with WDT reset from PD */
+    if (CLK->PMUSTS & CLK_PMUSTS_TMRWK_Msk) {
+        /* Per test, these reset reason flags will set with WKT reset. Clear them for this resolution. */
+        SYS_CLEAR_RST_SOURCE(SYS_RSTSTS_PINRF_Msk | SYS_RSTSTS_PORF_Msk);
+    }
+
     if (SYS_IS_POR_RST()) {
         reset_reason_cast = RESET_REASON_POWER_ON;
         reset_reason_count ++;
@@ -49,7 +55,8 @@ reset_reason_t hal_reset_reason_get(void)
         reset_reason_count ++;
     }
 
-    if (SYS_IS_WDT_RST()) {
+    /* Get around h/w limit with WDT reset from PD */
+    if (SYS_IS_WDT_RST() || (CLK->PMUSTS & CLK_PMUSTS_TMRWK_Msk)) {
         reset_reason_cast = RESET_REASON_WATCHDOG;
         reset_reason_count ++;
     }
@@ -103,6 +110,15 @@ uint32_t hal_reset_reason_get_raw(void)
 void hal_reset_reason_clear(void)
 {
     SYS_CLEAR_RST_SOURCE(SYS->RSTSTS);
+
+    /* Re-unlock protected clock setting */
+    SYS_UnlockReg();
+
+    /* Get around h/w limit with WDT reset from PD */
+    CLK->PMUSTS |= (CLK_PMUSTS_CLRWK_Msk | CLK_PMUSTS_TMRWK_Msk);
+
+    /* Lock protected registers */
+    SYS_LockReg();
 }
 
 #endif