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| 1 | +//===-- RISCVLateOpt.cpp - Late stage optimization ------------------------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +/// |
| 9 | +/// This file provides RISC-V specific target descriptions. |
| 10 | +/// |
| 11 | +//===----------------------------------------------------------------------===// |
| 12 | + |
| 13 | +#include "MCTargetDesc/RISCVMCTargetDesc.h" |
| 14 | +#include "RISCV.h" |
| 15 | +#include "RISCVInstrInfo.h" |
| 16 | +#include "RISCVSubtarget.h" |
| 17 | +#include "llvm/CodeGen/MachineBasicBlock.h" |
| 18 | +#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" |
| 19 | +#include "llvm/CodeGen/MachineDominators.h" |
| 20 | +#include "llvm/CodeGen/MachineInstrBuilder.h" |
| 21 | +#include "llvm/CodeGen/Passes.h" |
| 22 | +#include "llvm/CodeGen/RegisterScavenging.h" |
| 23 | +#include "llvm/MC/TargetRegistry.h" |
| 24 | +#include "llvm/Support/Debug.h" |
| 25 | + |
| 26 | +using namespace llvm; |
| 27 | + |
| 28 | +#define DEBUG_TYPE "riscv-late-opt" |
| 29 | +#define RISCV_LATE_OPT_NAME "RISC-V Late Stage Optimizations" |
| 30 | + |
| 31 | +namespace { |
| 32 | + |
| 33 | +struct RISCVLateOpt : public MachineFunctionPass { |
| 34 | + static char ID; |
| 35 | + |
| 36 | + RISCVLateOpt() : MachineFunctionPass(ID) {} |
| 37 | + |
| 38 | + StringRef getPassName() const override { return RISCV_LATE_OPT_NAME; } |
| 39 | + |
| 40 | + void getAnalysisUsage(AnalysisUsage &AU) const override { |
| 41 | + MachineFunctionPass::getAnalysisUsage(AU); |
| 42 | + } |
| 43 | + |
| 44 | + bool runOnMachineFunction(MachineFunction &Fn) override; |
| 45 | + |
| 46 | +private: |
| 47 | + bool trySimplifyCondBr(MachineInstr *MI, MachineBasicBlock *TBB, |
| 48 | + MachineBasicBlock *FBB, |
| 49 | + SmallVectorImpl<MachineOperand> &Cond) const; |
| 50 | + |
| 51 | + const RISCVInstrInfo *RII = nullptr; |
| 52 | +}; |
| 53 | +} // namespace |
| 54 | + |
| 55 | +char RISCVLateOpt::ID = 0; |
| 56 | +INITIALIZE_PASS(RISCVLateOpt, "riscv-late-opt", RISCV_LATE_OPT_NAME, false, |
| 57 | + false) |
| 58 | + |
| 59 | +bool RISCVLateOpt::trySimplifyCondBr( |
| 60 | + MachineInstr *MI, MachineBasicBlock *TBB, MachineBasicBlock *FBB, |
| 61 | + SmallVectorImpl<MachineOperand> &Cond) const { |
| 62 | + |
| 63 | + RISCVCC::CondCode CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); |
| 64 | + assert(CC != RISCVCC::COND_INVALID); |
| 65 | + |
| 66 | + // Right now we only care about LI (i.e. ADDI x0, imm) |
| 67 | + auto isLoadImm = [](const MachineInstr *MI, int64_t &Imm) -> bool { |
| 68 | + if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() && |
| 69 | + MI->getOperand(1).getReg() == RISCV::X0) { |
| 70 | + Imm = MI->getOperand(2).getImm(); |
| 71 | + return true; |
| 72 | + } |
| 73 | + return false; |
| 74 | + }; |
| 75 | + |
| 76 | + MachineBasicBlock *MBB = MI->getParent(); |
| 77 | + MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); |
| 78 | + // Either a load from immediate instruction or X0. |
| 79 | + auto isFromLoadImm = [&](const MachineOperand &Op, int64_t &Imm) -> bool { |
| 80 | + if (!Op.isReg()) |
| 81 | + return false; |
| 82 | + Register Reg = Op.getReg(); |
| 83 | + if (Reg == RISCV::X0) { |
| 84 | + Imm = 0; |
| 85 | + return true; |
| 86 | + } |
| 87 | + return Reg.isVirtual() && isLoadImm(MRI.getVRegDef(Reg), Imm); |
| 88 | + }; |
| 89 | + |
| 90 | + // Try and convert a conditional branch that can be evaluated statically |
| 91 | + // into an unconditional branch. |
| 92 | + MachineBasicBlock *Folded = nullptr; |
| 93 | + int64_t C0, C1; |
| 94 | + if (isFromLoadImm(Cond[1], C0) && isFromLoadImm(Cond[2], C1)) { |
| 95 | + switch (CC) { |
| 96 | + case RISCVCC::COND_INVALID: |
| 97 | + llvm_unreachable("Unexpected CC"); |
| 98 | + case RISCVCC::COND_EQ: { |
| 99 | + Folded = (C0 == C1) ? TBB : FBB; |
| 100 | + break; |
| 101 | + } |
| 102 | + case RISCVCC::COND_NE: { |
| 103 | + Folded = (C0 != C1) ? TBB : FBB; |
| 104 | + break; |
| 105 | + } |
| 106 | + case RISCVCC::COND_LT: { |
| 107 | + Folded = (C0 < C1) ? TBB : FBB; |
| 108 | + break; |
| 109 | + } |
| 110 | + case RISCVCC::COND_GE: { |
| 111 | + Folded = (C0 >= C1) ? TBB : FBB; |
| 112 | + break; |
| 113 | + } |
| 114 | + case RISCVCC::COND_LTU: { |
| 115 | + Folded = ((uint64_t)C0 < (uint64_t)C1) ? TBB : FBB; |
| 116 | + break; |
| 117 | + } |
| 118 | + case RISCVCC::COND_GEU: { |
| 119 | + Folded = ((uint64_t)C0 >= (uint64_t)C1) ? TBB : FBB; |
| 120 | + break; |
| 121 | + } |
| 122 | + } |
| 123 | + |
| 124 | + // Do the conversion |
| 125 | + // Build the new unconditional branch |
| 126 | + DebugLoc DL = MBB->findBranchDebugLoc(); |
| 127 | + if (Folded) { |
| 128 | + BuildMI(*MBB, MI, DL, RII->get(RISCV::PseudoBR)).addMBB(Folded); |
| 129 | + } else { |
| 130 | + MachineFunction::iterator Fallthrough = ++MBB->getIterator(); |
| 131 | + if (Fallthrough == MBB->getParent()->end()) |
| 132 | + return false; |
| 133 | + BuildMI(*MBB, MI, DL, RII->get(RISCV::PseudoBR)).addMBB(&*Fallthrough); |
| 134 | + } |
| 135 | + |
| 136 | + // Update successors of MBB-> |
| 137 | + if (Folded == TBB) { |
| 138 | + // If we're taking TBB, then the succ to delete is the fallthrough (if |
| 139 | + // it was a succ in the first place), or its the MBB from the |
| 140 | + // unconditional branch. |
| 141 | + if (!FBB) { |
| 142 | + MachineFunction::iterator Fallthrough = ++MBB->getIterator(); |
| 143 | + if (Fallthrough != MBB->getParent()->end() && |
| 144 | + MBB->isSuccessor(&*Fallthrough)) |
| 145 | + MBB->removeSuccessor(&*Fallthrough, true); |
| 146 | + } else { |
| 147 | + MBB->removeSuccessor(FBB, true); |
| 148 | + } |
| 149 | + } else if (Folded == FBB) { |
| 150 | + // If we're taking the fallthrough or unconditional branch, then the |
| 151 | + // succ to remove is the one from the conditional branch. |
| 152 | + MBB->removeSuccessor(TBB, true); |
| 153 | + } |
| 154 | + |
| 155 | + MI->eraseFromParent(); |
| 156 | + return true; |
| 157 | + } |
| 158 | + return false; |
| 159 | +} |
| 160 | + |
| 161 | +bool RISCVLateOpt::runOnMachineFunction(MachineFunction &Fn) { |
| 162 | + if (skipFunction(Fn.getFunction())) |
| 163 | + return false; |
| 164 | + |
| 165 | + auto &ST = Fn.getSubtarget<RISCVSubtarget>(); |
| 166 | + RII = ST.getInstrInfo(); |
| 167 | + |
| 168 | + bool Changed = false; |
| 169 | + |
| 170 | + for (MachineBasicBlock &MBB : Fn) { |
| 171 | + for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end(); |
| 172 | + MII != MIE;) { |
| 173 | + MachineInstr *MI = &*MII; |
| 174 | + // We may be erasing MI below, increment MII now. |
| 175 | + ++MII; |
| 176 | + if (!MI->isConditionalBranch()) |
| 177 | + continue; |
| 178 | + |
| 179 | + MachineBasicBlock *TBB, *FBB; |
| 180 | + SmallVector<MachineOperand, 4> Cond; |
| 181 | + if (!RII->analyzeBranch(MBB, TBB, FBB, Cond, /*AllowModify=*/false)) |
| 182 | + Changed |= trySimplifyCondBr(MI, TBB, FBB, Cond); |
| 183 | + } |
| 184 | + } |
| 185 | + |
| 186 | + return Changed; |
| 187 | +} |
| 188 | + |
| 189 | +/// Returns an instance of the Make Compressible Optimization pass. |
| 190 | +FunctionPass *llvm::createRISCVLateOptPass() { return new RISCVLateOpt(); } |
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