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‎README.md

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oneAPI-samples
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This is the readme.
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|Code sample name |Supported Intel(r) Architecture(s) |Description |
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|-----------------------|-------------------------------------------|---------------|
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|DirectPrograming/ |
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|../DPC++/CombinationalLogic/Mandelbrot |GPU, CPU |Example of a fractal in mathematics |
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|../DPC++/CombinationalLogic/Sepia-filter |GPU, CPU |Color image conversion using 1D range |
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|../DPC++/DenseLinearAlgebra/Complex_mult |GPU, CPU |Complex number Multiplication |
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|../DPC++/DenseLinearAlgebra/Matrix_mul |GPU, CPU |Simple program that multiplies two large matrices in parallel using DPC++, OpenMP and MKL |
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|../DPC++/DenseLinearAlgebra/Simple-add |FPGA, GPU, CPU |Simple Add program |
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|../DPC++/DenseLinearAlgebra/Vector-add |FPGA, GPU, CPU |Simple Vector add program |
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|../DPC++/GraphTraversal/Bitonic-sort |GPU, CPU |Implementation of bitonic sort using DPC++. |
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|../DPC++/ParallelPatterns/Dpc_reduce |GPU, CPU |A simple program that calculates pi, implemented using C++ and DPC++. |
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|../DPC++/SpectralMethods/Discrete-cosine-transform |GPU, CPU |Image processing algorithm used in JPEG compression |
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|../DPC++/StructuredGrids/1d_HeatTransfer |GPU, CPU |A simulation of one dimensional heat transfer process using DPC++. |
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|../DPC++/StructuredGrids/ISO2DFD_DPCPP |GPU, CPU |A simple finite difference stencil kernel for solving 2D acoustic isotropic wave equation using DPC++ |
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|../DPC++/StructuredGrids/ISO3DFD_DPCPP |GPU, CPU |A finite difference stencil kernel for solving 3D acoustic isotropic wave equation using DPC++ |
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|../DPC++/StructuredGrids/Particle-diffusion |GPU, CPU |A simple implementation of a Monte Carlo simulation of the diffusion of water molecules in tissue |
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|../C++/CombinationalLogic/Mandelbrot |CPU |Demonstrates how to accelerate Mandelbrot performance with SIMD and parallelization using OpenMP*. |
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|../C++/CompilerInfrastructure/Intrinsics |CPU |Shows how to utilize the intrinsics supported by C++ compiler in a variety of applications. |
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|../C++/GraphTraversal/Mergesort |CPU |Shows how to accelerate scalar merge sort program using OpenMP tasks |
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|../FPGA/FPGATutorials/BestPractices/double_buffering |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/BestPractices/local_memory_cache |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/BestPractices/n_way_buffering |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/BestPractices/remove_loop_carried_dependency |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/BestPractices/triangular_loop |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/Compilation/compile_flow |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/Compilation/device_link |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/Compilation/use_library |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/LoopAttributes/loop_ivdep |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/LoopAttributes/loop_unroll |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/LoopAttributes/max_concurrency |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/Other/fpga_register |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/Other/no_accessor_aliasing |FPGA, CPU |See details under FPGA Tutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/Other/system_profiling |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/MemoryAttributes/memory_attributes_overview |FPGA, CPU |See details under FPGATutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/Pipes/pipe_array |FPGA |See details under FPGATutorials |
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|../FPGA/FPGATutorials/FPGAExtensions/Pipes/pipes |FPGA |See details under FPGATutorials |
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|../FPGA/FPGAExampleDesigns/crr |FPGA, CPU |See details under FPGAExampleDesigns |
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|../FPGA/FPGAExampleDesigns/gzip |FPGA |See details under FPGAExampleDesigns |
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|../FPGA/FPGAExampleDesigns/grd |FPGA, CPU |See details under FPGAExampleDesigns |
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|Libraries |
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|../oneDPL/Gamma-correction |GPU, CPU |gamma correction using Parallel STL |
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|../oneDPL/Stable_sort_by_key |GPU, CPU |stable sort by key using counting_iterator and zip_iterator |
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|../oneVPL/hello-decode |CPU |shows how to use oneVPL to perform a simple video decode |
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|../oneVPL/hello-encode |CPU |shows how to use oneVPL to perform a simple video encode |
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|Tools |
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|../ApplicationDebugger/Debugger/array-transform |GPU, CPU |Array transform |
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|../IoTConnectionTools/Analog-in |CPU |Analog pin input example using Eclipse* MRAA |
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|../IoTConnectionTools/Digital In |CPU |GPIO pin input example using Eclipse* MRAA |
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|../IoTConnectionTools/Digital Out |CPU |GPIO pin output example using Eclipse* MRAA |
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|../IoTConnectionTools/Hello IoT World |CPU |Basic example that prints the compiler used during build |
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|../IoTConnectionTools/Interrupt |CPU |Interrupt Service Routine example using Eclipse* MRAA |
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|../IoTConnectionTools/Onboard Blink |CPU |Built-in LED blink for common IoT boards using Eclipse* MRAA |
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|../IoTConnectionTools/PWM |CPU |Pulse Width Modulation pin output using Eclipse* MRAA |
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|../IoTConnectionTools/Up2 LEDs |CPU |Built-in LED example for UP* Squared using Eclipse* MRAA |
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|../SystemDebug/System Debug Sample Build |UEFI |Basic example that showcases the features of the Intel® System Debugger |
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#License
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The code samples are licensed under MIT license
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#Known issues or limitations
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##On Windows Platform
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1. If you are using Visual Studio 2019, Visual Studio 2019 version 16.3.0 or newer is required.
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2. To build samples on Windows, the required Windows SDK is ver. 10.0.17763.0.
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1. If the SDK is not installed, use the following instructions below to avoid build failure:
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1. Open the "code sample's" .sln from within Visual Studio 2017 or 2019,
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2. Right-click on the project name in "Solution Explorer" and select "Properties"
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2. The project property dialog opens.
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1. Select the "General" tab on the left,
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2. Select on the right side of the dialog box "Windows SDK Version"(2nd Item".
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3. Click on the drop-down icon to select a version that is installed on your system.
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4. click on [Ok] to save.
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3. Now you should be able to build the code sample.
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4. For beta, FPGA samples support Windows through FPGA-emulator.
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5. If you encounter a compilation error like below when building a sample program, one reason is that the directory path of the sample is too long; the work around is to move the sample to a directory like "c:\temp\sample_name".
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* Error MSB6003 The specified task executable "dpcpp-cl.exe" could not be run ......
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