Merge branch 'oneapi-src:development' into development

Author: eleemhui

AI-and-Analytics/End-to-end-Workloads/JobRecommendationSystem/requirements.txt

@@ -1,10 +1,10 @@
-ipykernel
-matplotlib
-sentence_transformers
-transformers 
-datasets 
-accelerate 
-wordcloud  
-spacy 
-jinja2
+ipykernel
+matplotlib
+sentence-transformers
+transformers
+datasets
+accelerate
+wordcloud
+spacy
+jinja2
 nltk

AI-and-Analytics/Features-and-Functionality/IntelTensorFlow_AMX_BF16_Inference/requirements.txt

@@ -1,6 +1,6 @@
 notebook
 Pillow
-tensorflow_hub==0.16
+tensorflow-hub==0.16
 requests
 py-cpuinfo
 

AI-and-Analytics/Features-and-Functionality/IntelTensorFlow_Enabling_Auto_Mixed_Precision_for_TransferLearning/requirements.txt

@@ -1,5 +1,5 @@
-neural_compressor==2.4.1
+neural-compressor==2.4.1
 Pillow
 py-cpuinfo
 requests
-tensorflow_hub==0.16.0
+tensorflow-hub==0.16.0

AI-and-Analytics/Features-and-Functionality/IntelTensorFlow_Enabling_Auto_Mixed_Precision_for_TransferLearning/scripts/plot.py

@@ -8,8 +8,10 @@
         throughput = line.split(': ')[1]
         throughput_list.append(float(throughput))
 
-print("Throughput list: ", throughput_list)
-speedup = float(throughput_list[1])/float(throughput_list[0])
-print("Speedup : ", speedup)
-df = pd.DataFrame({'pretrained_model':['saved model', 'optimized model'], 'Speedup':[1, speedup]})
-ax = df.plot.bar( x='pretrained_model', y='Speedup', rot=0)
+if len(throughput_list) == 2:
+    speedup = float(throughput_list[1])/float(throughput_list[0])
+    print("Speedup : ", speedup)
+    df = pd.DataFrame({'pretrained_model':['saved model', 'optimized model'], 'Speedup':[1, speedup]})
+    ax = df.plot.bar( x='pretrained_model', y='Speedup', rot=0)
+else:
+    print("Incorrect data size to calculate speedup")

AI-and-Analytics/Features-and-Functionality/IntelTransformers_Quantization/requirements.txt

@@ -1,7 +1,7 @@
 accelerate==0.29.3
 datasets==2.09.0
 intel-extension-for-transformers==1.4.1
-neural_speed==1.0
+neural-speed==1.0
 peft==0.10.0
 sentencepiece
 transformers==4.38.0

AI-and-Analytics/Getting-Started-Samples/INC-Quantization-Sample-for-PyTorch/requirements.txt

@@ -1,3 +1,3 @@
-neural_compressor==2.1
+neural-compressor==2.1
 transformers>=4.27.4
-datasets>=2.4.0
+datasets>=2.4.0

AI-and-Analytics/Getting-Started-Samples/Intel_Extension_For_TensorFlow_GettingStarted/requirements.txt

@@ -1,3 +1,3 @@
-tensorflow_hub
+tensorflow-hub
 ipykernel
 matplotlib

DirectProgramming/C++/ParallelPatterns/openmp_reduction/README.md

@@ -23,7 +23,7 @@ This example demonstrates how to perform reduction by using the CPU in serial mo
 
 This code shows how to use OpenMP on the CPU host as well as using target offload capabilities.
 
-The different modes use a simple calculation using the well known mathematical formula that states if one integrates from 0 to 1 over the function, $(4.0/(1+x*x))dx$, the answer is pi. One can approximate this integral by summing up the area of a large number of rectangles over this same range.
+The different modes use a simple calculation using the well known mathematical formula, $\int_{0}^{1} \frac{4}{1 + x^2}\\mathrm{d}x$, the answer is pi. One can approximate this integral by summing up the area of a large number of rectangles over this same range.
 
 Each of the different functions calculates pi by breaking the range into many tiny rectangles and then summing up the results.
 

DirectProgramming/C++SYCL/DenseLinearAlgebra/simple-add/README.md

@@ -15,27 +15,16 @@ The `Simple Add` sample is a simple program that adds two large vectors of integ
 The basic SYCL implementations explained in the sample includes device selector,
 USM, buffer, accessor, kernel, and command groups.
 
->**Note**: See the `Base: Vector Add` sample to examine another getting started sample you can use to learn more about using the Intel® oneAPI Toolkits to develop SYCL-compliant applications for CPU, GPU, and FPGA devices.
+>**Note**: See the `Base: Vector Add` sample to examine another getting started sample you can use to learn more about using the Intel® oneAPI Toolkits to develop SYCL-compliant applications for CPU and GPU devices.
 
 ## Prerequisites
 
 | Optimized for      | Description
 |:---                |:---
 | OS                 | Ubuntu* 18.04 <br> Windows* 10, 11
-| Hardware           | GEN9 or newer <br> Intel® Agilex® 7, Arria® 10, and Stratix® 10 FPGAs
+| Hardware           | GEN9 or newer
 | Software           | Intel® oneAPI DPC++/C++ Compiler
 
-
-> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for CPU, GPU, FPGA emulation, generating FPGA reports and generating RTL for FPGAs, there are extra software requirements for the FPGA simulation flow and FPGA compiles.
->
-> For using the simulator flow, Intel® Quartus® Prime Pro Edition and one of the following simulators must be installed and accessible through your PATH:
-> - Questa*-Intel® FPGA Edition
-> - Questa*-Intel® FPGA Starter Edition
-> - ModelSim® SE
->
-> When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH.
-> **Warning** Make sure you add the device files associated with the FPGA that you are targeting to your Intel® Quartus® Prime installation.
-
 ## Key Implementation Details
 
 This sample provides examples of both buffers and USM implementations for simple side-by-side comparison.
@@ -105,20 +94,7 @@ To learn more about the extensions and how to configure the oneAPI environment,
    cmake .. -DUSM=1
    ```
 
-   > **Note**: When building for FPGAs, the default FPGA family will be used (Intel® Agilex® 7).
-   > You can change the default target by using the command:
-   >  ```
-   >  cmake .. -DFPGA_DEVICE=<FPGA device family or FPGA part number>
-   >  ```
-   >
-   > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command:
-   >  ```
-   >  cmake .. -DFPGA_DEVICE=<board-support-package>:<board-variant>
-   >  ```
-   >
-   > You will only be able to run an executable on the FPGA if you specified a BSP.
-
-#### Build for CPU and GPU
+#### Build
 
 1. Build the program.
    ```
@@ -129,33 +105,6 @@ To learn more about the extensions and how to configure the oneAPI environment,
    make clean
    ```
 
-#### Build for FPGA
-
-1. Compile for FPGA emulation.
-   ```
-   make fpga_emu
-   ```
-2. Compile for simulation (fast compile time, targets simulator FPGA device):
-   ```
-   make fpga_sim
-   ```
-3. Generate HTML performance reports.
-   ```
-   make report
-   ```
-   The reports reside at `simple-add_report.prj/reports/report.html`.
-
-4. Compile the program for FPGA hardware. (Compiling for hardware can take a long
-time.)
-   ```
-   make fpga
-   ```
-
-5. Clean the program. (Optional)
-   ```
-   make clean
-   ```
-
 ### On Windows*
 
 #### Configure the build system
@@ -177,20 +126,7 @@ time.)
    cmake -G "NMake Makefiles" .. -DUSM=1
    ```
 
-   > **Note**: When building for FPGAs, the default FPGA family will be used (Intel® Agilex® 7).
-   > You can change the default target by using the command:
-   >  ```
-   >  cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=<FPGA device family or FPGA part number>
-   >  ```
-   >
-   > Alternatively, you can target an explicit FPGA board variant and BSP by using the following command:
-   >  ```
-   >  cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=<board-support-package>:<board-variant>
-   >  ```
-   >
-   > You will only be able to run an executable on the FPGA if you specified a BSP.
-
-#### Build for CPU and GPU
+#### Build
 
 1. Build the program.
    ```
@@ -201,35 +137,6 @@ time.)
    nmake clean
    ```
 
-#### Build for FPGA
-
->**Note**: Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support.
-
-1. Compile for FPGA emulation.
-   ```
-   nmake fpga_emu
-   ```
-2. Compile for simulation (fast compile time, targets simulator FPGA device):
-   ```
-   nmake fpga_sim
-   ```
-3. Generate HTML performance reports.
-   ```
-   nmake report
-   ```
-The reports reside at `simple-add_report.prj/reports/report.html`.
-
-4. Compile the program for FPGA hardware. (Compiling for hardware can take a long
-time.)
-   ```
-   nmake fpga
-   ```
-
-5. Clean the program. (Optional)
-   ```
-   nmake clean
-   ```
-
 #### Troubleshooting
 
 If an error occurs, you can get more details by running `make` with
@@ -243,39 +150,16 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic
 
 ### On Linux
 
-#### Run for CPU and GPU
-
 1. Change to the output directory.
 
 2. Run the program for Unified Shared Memory (USM) and buffers.
    ```
    ./simple-add-buffers
    ./simple-add-usm
    ```
-#### Run for FPGA
-
-1. Change to the output directory.
-
-2. Run for FPGA emulation.
-   ```
-   ./simple-add-buffers.fpga_emu
-   ./simple-add-usm.fpga_emu
-   ```
-3. Run on FPGA simulator.
-   ```
-   CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./simple-add-buffers.fpga_sim
-   CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./simple-add-usm.fpga_sim
-   ```
-4. Run on FPGA hardware (only if you ran `cmake` with `-DFPGA_DEVICE=<board-support-package>:<board-variant>`).
-   ```
-   ./simple-add-buffers.fpga
-   ./simple-add-usm.fpga
-   ```
 
 ### On Windows
 
-#### Run for CPU and GPU
-
 1. Change to the output directory.
 
 2. Run the program for Unified Shared Memory (USM) and buffers.
@@ -284,31 +168,9 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic
    simple-add-buffers.exe
    ```
 
-#### Run for FPGA
-
-1. Change to the output directory.
-
-2. Run for FPGA emulation.
-   ```
-   simple-add-buffers.fpga_emu.exe
-   simple-add-usm.fpga_emu.exe
-   ```
-3. Run on FPGA simulator.
-   ```
-   set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1
-   simple-add-buffers.fpga_sim.exe
-   simple-add-usm.fpga_sim.exe
-   set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=
-   ```
-4. Run on FPGA hardware (only if you ran `cmake` with `-DFPGA_DEVICE=<board-support-package>:<board-variant>`).
-   ```
-   simple-add-buffers.fpga.exe
-   simple-add-usm.fpga.exe
-   ```
-
 ### Build and Run the `Simple Add` Sample in Intel® DevCloud (Optional)
 
-When running a sample in the Intel® DevCloud, you must specify the compute node (CPU, GPU, FPGA) and whether to run in batch or interactive mode.
+When running a sample in the Intel® DevCloud, you must specify the compute node (CPU, GPU) and whether to run in batch or interactive mode.
 
 >**Note**: Since Intel® DevCloud for oneAPI includes the appropriate development environment already configured, you do not need to set environment variables.
 
@@ -328,19 +190,9 @@ qsub  -I  -l nodes=1:gpu:ppn=2 -d .
   |:---                      |:---
   |GPU	                     |`qsub -l nodes=1:gpu:ppn=2 -d .`
   |CPU	                     |`qsub -l nodes=1:xeon:ppn=2 -d .`
-  |FPGA Compile Time         |`qsub -l nodes=1:fpga_compile:ppn=2 -d .`
-  |FPGA Runtime (Arria 10)   |`qsub -l nodes=1:fpga_runtime:arria10:ppn=2 -d .`
-
 
 >**Note**: For more information on how to specify compute nodes, read *[Launch and manage jobs](https://devcloud.intel.com/oneapi/documentation/job-submission/)* in the Intel® DevCloud for oneAPI Documentation.
 
-Only `fpga_compile` nodes support compiling to FPGA. When compiling for FPGA hardware, increase the job timeout to **24 hours**.
-
-Executing programs on FPGA hardware is only supported on `fpga_runtime` nodes of the appropriate type, such as `fpga_runtime:arria10`.
-
-Neither compiling nor executing programs on FPGA hardware are supported on the login nodes. For more information, see the Intel® DevCloud for oneAPI [*Intel® oneAPI Base Toolkit Get Started*](https://devcloud.intel.com/oneapi/get_started/) page.
-
-
 ## Example Output
 ```
 simple-add output snippet changed to: