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[CI] Add more qemu configs
Signed-off-by: Krzysztof Filipek <[email protected]>
1 parent a85037f commit 4b840d7

11 files changed

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-1
lines changed

‎scripts/qemu/configs/default.xml

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@@ -1,8 +1,20 @@
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<!-- SPDX-License-Identifier: BSD-2-Clause
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# Copyright (C) 2024 Intel Corporation.
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-->
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<!--
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+________________+ +________________+ +_________________+
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| Cell 0 | | Cell 1 | | Cell 2 |
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| CPUs 0-1: 0-1 | | CPUs 2-3: 2-3 | | No specific CPUs|
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| Memory: 1100MiB| | Memory: 1200MiB| | Memory: 1200MiB |
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+________________+ +________________+ +_________________+
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| 10 | 10 | 10
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| 20 | 20 | 17
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| 17 | 28 | 28
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v v v
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-->
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<domain type='qemu'>
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<name>CascadeLake</name>
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<name>Default</name>
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<os>
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<type arch='x86_64' machine='pc'>hvm</type>
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</os>

‎scripts/qemu/configs/sock_2_var1.xml

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<!-- SPDX-License-Identifier: BSD-2-Clause
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# Copyright (C) 2020 - 2024 Intel Corporation.
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-->
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<!--
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+________________+ +________________+ +_________________+
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| Cell 0 | | Cell 1 | | Cell 2 |
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| CPUs 0-1: 0-1 | | CPUs 2-3: 2-3 | | No specific CPUs|
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| Memory: 256MiB | | Memory: 512MiB | | Memory: 2560MiB |
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+________________+ +________________+ +_________________+
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| 10 | 10 | 10
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| 20 | 20 | 17
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| 17 | 28 | 28
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v v v
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-->
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<domain type='qemu'>
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<name>Sockets2Var1</name>
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<os>
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<type arch='x86_64' machine='pc'>hvm</type>
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</os>
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<vcpu placement='static'>4</vcpu>
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<cpu>
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<topology sockets='2' dies='1' cores='2' threads='1'/>
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<numa>
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<cell id='0' cpus='0-1' memory='256' unit='MiB'>
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<distances>
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<sibling id='0' value='10'/>
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<sibling id='1' value='20'/>
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<sibling id='2' value='17'/>
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</distances>
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</cell>
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<cell id='1' cpus='2-3' memory='512' unit='MiB'>
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<distances>
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<sibling id='0' value='20'/>
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<sibling id='1' value='10'/>
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<sibling id='2' value='28'/>
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</distances>
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</cell>
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<cell id='2' memory='2560' unit='MiB'>
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<distances>
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<sibling id='0' value='17'/>
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<sibling id='1' value='28'/>
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<sibling id='2' value='10'/>
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</distances>
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</cell>
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</numa>
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</cpu>
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</domain>

‎scripts/qemu/configs/sock_2_var1_hmat.xml

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<!-- SPDX-License-Identifier: BSD-2-Clause
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# Copyright (C) 2021 - Intel Corporation.
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-->
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<!--
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+________________+ +________________+ +_________________+
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| Cell 0 | | Cell 1 | | Cell 2 |
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| CPUs 0-1: 0-1 | | CPUs 2-3: 2-3 | | No specific CPUs|
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| Memory: 1152MiB| | Memory: 1152MiB| | Memory: 1260MiB |
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+________________+ +________________+ +_________________+
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| 10 | 10 | 10
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| 20 | 20 | 17
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| 17 | 28 | 28
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v v v
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-->
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<domain type='qemu'>
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<name>Sockets2Var1HMAT</name>
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<os>
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<type arch='x86_64' machine='pc'>hvm</type>
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</os>
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<vcpu placement='static'>4</vcpu>
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<cpu>
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<topology sockets='2' dies='1' cores='2' threads='1'/>
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<numa>
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<cell id='0' cpus='0-1' memory='1152' unit='MiB'>
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<distances>
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<sibling id='0' value='10'/>
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<sibling id='1' value='20'/>
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<sibling id='2' value='17'/>
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</distances>
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</cell>
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<cell id='1' cpus='2-3' memory='1152' unit='MiB'>
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<distances>
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<sibling id='0' value='20'/>
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<sibling id='1' value='10'/>
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<sibling id='2' value='28'/>
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</distances>
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</cell>
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<cell id='2' memory='1260' unit='MiB'>
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<distances>
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<sibling id='0' value='17'/>
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<sibling id='1' value='28'/>
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<sibling id='2' value='10'/>
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</distances>
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</cell>
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<interconnects>
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<latency initiator='0' target='0' type='access' value='72'/>
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<bandwidth initiator='0' target='0' type='access' value='111000' unit='MiB'/>
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<latency initiator='0' target='1' type='access' value='133'/>
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<bandwidth initiator='0' target='1' type='access' value='33770' unit='MiB'/>
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<latency initiator='0' target='2' type='access' value='176'/>
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<bandwidth initiator='0' target='2' type='access' value='25600' unit='MiB'/>
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<latency initiator='1' target='1' type='access' value='72'/>
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<bandwidth initiator='1' target='1' type='access' value='111000' unit='MiB'/>
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<latency initiator='1' target='2' type='access' value='240'/>
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<bandwidth initiator='1' target='2' type='access' value='840' unit='MiB'/>
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</interconnects>
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</numa>
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</cpu>
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</domain>

‎scripts/qemu/configs/sock_2_var2.xml

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<!-- SPDX-License-Identifier: BSD-2-Clause
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# Copyright (C) 2021 - 2024 Intel Corporation.
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-->
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<!--
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+________________+ +________________+ +_________________+
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| Cell 0 | | Cell 1 | | Cell 2 |
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| CPUs 0-1: 0-1 | | CPUs 2-3: 2-3 | | No specific CPUs|
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| Memory: 256MiB | | Memory: 512MiB | | Memory: 2560MiB |
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+________________+ +________________+ +_________________+
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| 10 | 10 | 10
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| 20 | 20 | 17
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| 28 | 17 | 28
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v v v
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-->
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<domain type='qemu'>
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<name>Sockets2Var2</name>
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<os>
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<type arch='x86_64' machine='pc'>hvm</type>
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</os>
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<vcpu placement='static'>4</vcpu>
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<cpu>
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<topology sockets='2' dies='1' cores='2' threads='1'/>
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<numa>
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<cell id='0' cpus='0-1' memory='256' unit='MiB'>
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<distances>
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<sibling id='0' value='10'/>
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<sibling id='1' value='20'/>
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<sibling id='2' value='28'/>
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</distances>
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</cell>
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<cell id='1' cpus='2-3' memory='512' unit='MiB'>
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<distances>
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<sibling id='0' value='20'/>
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<sibling id='1' value='10'/>
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<sibling id='2' value='17'/>
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</distances>
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</cell>
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<cell id='2' memory='2560' unit='MiB'>
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<distances>
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<sibling id='0' value='28'/>
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<sibling id='1' value='17'/>
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<sibling id='2' value='10'/>
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</distances>
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</cell>
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</numa>
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</cpu>
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</domain>

‎scripts/qemu/configs/sock_2_var2_hmat.xml

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<!-- SPDX-License-Identifier: BSD-2-Clause
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# Copyright (C) 2021 - 2024 Intel Corporation.
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-->
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<!--
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+________________+ +________________+ +_________________+
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| Cell 0 | | Cell 1 | | Cell 2 |
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| CPUs 0-1: 0-1 | | CPUs 2-3: 2-3 | | No specific CPUs|
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| Memory: 1152MiB| | Memory: 1152MiB| | Memory: 1792MiB |
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+________________+ +________________+ +_________________+
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| 10 | 10 | 10
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| 20 | 20 | 17
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| 28 | 17 | 28
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v v v
15+
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-->
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<domain type='qemu'>
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<name>Sockets2Var2HMAT</name>
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<os>
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<type arch='x86_64' machine='pc'>hvm</type>
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</os>
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<vcpu placement='static'>4</vcpu>
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<cpu>
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<topology sockets='2' dies='1' cores='2' threads='1'/>
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<numa>
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<cell id='0' cpus='0-1' memory='1152' unit='MiB'>
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<distances>
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<sibling id='0' value='10'/>
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<sibling id='1' value='20'/>
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<sibling id='2' value='28'/>
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</distances>
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</cell>
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<cell id='1' cpus='2-3' memory='1152' unit='MiB'>
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<distances>
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<sibling id='0' value='20'/>
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<sibling id='1' value='10'/>
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<sibling id='2' value='17'/>
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</distances>
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</cell>
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<cell id='2' memory='1792' unit='MiB'>
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<distances>
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<sibling id='0' value='28'/>
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<sibling id='1' value='17'/>
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<sibling id='2' value='10'/>
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</distances>
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</cell>
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<interconnects>
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<latency initiator='0' target='0' type='access' value='72'/>
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<bandwidth initiator='0' target='0' type='access' value='111000' unit='MiB'/>
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<latency initiator='0' target='1' type='access' value='133'/>
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<bandwidth initiator='0' target='1' type='access' value='33770' unit='MiB'/>
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<latency initiator='0' target='2' type='access' value='240'/>
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<bandwidth initiator='0' target='2' type='access' value='840' unit='MiB'/>
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<latency initiator='1' target='1' type='access' value='72'/>
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<bandwidth initiator='1' target='1' type='access' value='111000' unit='MiB'/>
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<latency initiator='1' target='2' type='access' value='176'/>
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<bandwidth initiator='1' target='2' type='access' value='25600' unit='MiB'/>
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</interconnects>
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</numa>
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</cpu>
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</domain>

‎scripts/qemu/configs/sock_2_var3.xml

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<!-- SPDX-License-Identifier: BSD-2-Clause
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# Copyright (C) 2021 - 2024 Intel Corporation.
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-->
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<!--
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+________________+ +________________+
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| Cell 0 | | Cell 1 |
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| CPUs 0-1: 0_1 | | CPUs 2-3: 2-3 |
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| Memory: 256MiB | | Memory: 512MiB |
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+________________+ +________________+
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| 10 | 10
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| 20 | 20
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| 17 | 28
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| 28 | 17
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v v
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+________________+ +________________+
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| Cell 2 | | Cell 3 |
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| Memory: 2560MiB| | Memory: 2560MiB|
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+________________+ +________________+
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-->
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<domain type='qemu'>
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<name>Sockets2Var3</name>
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<os>
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<type arch='x86_64' machine='pc'>hvm</type>
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</os>
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<vcpu placement='static'>4</vcpu>
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<cpu>
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<topology sockets='2' dies='1' cores='2' threads='1'/>
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<numa>
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<cell id='0' cpus='0-1' memory='256' unit='MiB'>
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<distances>
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<sibling id='0' value='10'/>
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<sibling id='1' value='20'/>
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<sibling id='2' value='17'/>
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<sibling id='3' value='28'/>
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</distances>
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</cell>
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<cell id='1' cpus='2-3' memory='512' unit='MiB'>
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<distances>
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<sibling id='0' value='20'/>
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<sibling id='1' value='10'/>
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<sibling id='2' value='28'/>
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<sibling id='3' value='17'/>
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</distances>
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</cell>
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<cell id='2' memory='2560' unit='MiB'>
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<distances>
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<sibling id='0' value='17'/>
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<sibling id='1' value='28'/>
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<sibling id='2' value='10'/>
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<sibling id='3' value='28'/>
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</distances>
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</cell>
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<cell id='3' memory='2560' unit='MiB'>
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<distances>
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<sibling id='0' value='28'/>
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<sibling id='1' value='17'/>
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<sibling id='2' value='28'/>
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<sibling id='3' value='10'/>
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</distances>
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</cell>
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</numa>
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</cpu>
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</domain>

‎scripts/qemu/configs/sock_2_var3_hmat.xml

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<!-- SPDX-License-Identifier: BSD-2-Clause
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# Copyright (C) 2021 - 2024 Intel Corporation.
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-->
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<!--
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+________________+ +________________+
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| Cell 0 | | Cell 1 |
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| CPUs 0-1: 0-1 | | CPUs 2-3: 2-3 |
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| Memory: 1024MiB| | Memory: 1024MiB|
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+________________+ +________________+
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| 10 | 10
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| 20 | 20
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| 17 | 28
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| 28 | 17
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v v
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+________________+ +________________+
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| Cell 2 | | Cell 3 |
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| Memory: 1792MiB| | Memory: 1792MiB|
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+________________+ +________________+
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-->
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<domain type='qemu'>
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<name>Sockets2Var3HMAT</name>
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<os>
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<type arch='x86_64' machine='pc'>hvm</type>
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</os>
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<vcpu placement='static'>4</vcpu>
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<cpu>
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<topology sockets='2' dies='1' cores='2' threads='1'/>
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<numa>
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<cell id='0' cpus='0-1' memory='1024' unit='MiB'>
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<distances>
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<sibling id='0' value='10'/>
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<sibling id='1' value='20'/>
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<sibling id='2' value='17'/>
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<sibling id='3' value='28'/>
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</distances>
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</cell>
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<cell id='1' cpus='2-3' memory='1024' unit='MiB'>
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<distances>
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<sibling id='0' value='20'/>
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<sibling id='1' value='10'/>
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<sibling id='2' value='28'/>
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<sibling id='3' value='17'/>
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</distances>
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</cell>
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<cell id='2' memory='1792' unit='MiB'>
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<distances>
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<sibling id='0' value='17'/>
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<sibling id='1' value='28'/>
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<sibling id='2' value='10'/>
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<sibling id='3' value='28'/>
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</distances>
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</cell>
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<cell id='3' memory='1792' unit='MiB'>
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<distances>
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<sibling id='0' value='28'/>
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<sibling id='1' value='17'/>
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<sibling id='2' value='28'/>
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<sibling id='3' value='10'/>
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</distances>
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</cell>
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<interconnects>
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<latency initiator='0' target='0' type='access' value='72'/>
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<bandwidth initiator='0' target='0' type='access' value='111000' unit='MiB'/>
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<latency initiator='0' target='1' type='access' value='133'/>
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<bandwidth initiator='0' target='1' type='access' value='33770' unit='MiB'/>
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<latency initiator='0' target='2' type='access' value='176'/>
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<bandwidth initiator='0' target='2' type='access' value='25600' unit='MiB'/>
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<latency initiator='0' target='3' type='access' value='240'/>
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<bandwidth initiator='0' target='3' type='access' value='840' unit='MiB'/>
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<latency initiator='1' target='1' type='access' value='72'/>
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<bandwidth initiator='1' target='1' type='access' value='111000' unit='MiB'/>
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<latency initiator='1' target='2' type='access' value='240'/>
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<bandwidth initiator='1' target='2' type='access' value='840' unit='MiB'/>
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<latency initiator='1' target='3' type='access' value='176'/>
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<bandwidth initiator='1' target='3' type='access' value='25600' unit='MiB'/>
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</interconnects>
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</numa>
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</cpu>
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</domain>

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