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| 1 | +Glossary |
| 2 | +========================================================== |
| 3 | + |
| 4 | +Homogeneous Memory |
| 5 | + A collection of memory composed of a single memory type, managed by a singular |
| 6 | + driver using a uniform approach. |
| 7 | + |
| 8 | +Heterogeneous Memory |
| 9 | + A set of memory composed of multiple types of memory technologies, each |
| 10 | + requiring distinct handling approaches often managed by separate drivers. |
| 11 | + |
| 12 | +Memory Tiering |
| 13 | + An organization and hierarchy of different types of memory storage within a |
| 14 | + system, with each type of memory having distinct characteristics, performance, |
| 15 | + and cost attributes. These memory tiers are typically organized in a |
| 16 | + hierarchy, with faster, more expensive memory located closer to the processor |
| 17 | + and slower, less expensive memory located further away. |
| 18 | + |
| 19 | +Memory Access Initiator |
| 20 | + A component in a computer system that initiates or requests access to the |
| 21 | + computer's memory subsystem. This could be a CPU, GPU, or other I/O and cache |
| 22 | + devices. |
| 23 | + |
| 24 | +Memory Target |
| 25 | + Any part of the memory subsystem that can handle memory access requests. This |
| 26 | + could be the OS memory (RAM), video memory that resides on the graphics |
| 27 | + cards, memory caches, storage, external memory devices connected using |
| 28 | + CXL.mem protocol, etc. |
| 29 | + |
| 30 | +Memory Page |
| 31 | + A fixed-length contiguous block of virtual memory, described by a single |
| 32 | + entry in the page table. It is the smallest unit of data for memory |
| 33 | + management in a virtual memory operating system. |
| 34 | + |
| 35 | +Enlightened Application |
| 36 | + An application that explicitly manages data allocation distribution among |
| 37 | + memory tiers and further data migration. |
| 38 | + |
| 39 | +Unenlightened Application |
| 40 | + An application that coexists with the underlying infrastructure (OS, |
| 41 | + frameworks, libraries) that offers various memory tiering and migration |
| 42 | + solutions without any code modifications. |
| 43 | + |
| 44 | +Memory Pool |
| 45 | + A memory management technique used in computer programming and software |
| 46 | + development, where fixed-size blocks of memory are preallocated using one or |
| 47 | + more memory providers and then divided into smaller, fixed-size blocks or |
| 48 | + chunks. These smaller blocks are then allocated and deallocated by a pool |
| 49 | + allocator depending on the needs of the program or application. Thanks to |
| 50 | + low fragmentation and constant allocation time, memory pools are used to |
| 51 | + optimize memory allocation and deallocation in scenarios where efficiency |
| 52 | + and performance are critical. |
| 53 | + |
| 54 | +Pool Allocator |
| 55 | + A memory allocator type used to efficiently manage memory pools. |
| 56 | + |
| 57 | +Memory Provider |
| 58 | + A software component responsible for supplying memory or managing memory |
| 59 | + targets. A single memory provider kind can efficiently manage the memory |
| 60 | + operations for one or multiple devices within the system or other memory |
| 61 | + sources like file-backed or user-provided memory. |
| 62 | + |
| 63 | +High Bandwidth Memory (HBM) |
| 64 | + A high-speed computer memory. It is used in conjunction with high-performance |
| 65 | + graphics accelerators, network devices, and high-performance data centers, as |
| 66 | + on-package cache on-package RAM in CPUs, FPGAs, supercomputers, etc. |
| 67 | + |
| 68 | +Compute Express Link (CXL_) |
| 69 | + An open standard for high-speed, high-capacity central processing unit |
| 70 | + (CPU)-to-device and CPU-to-memory connections, designed for high-performance |
| 71 | + data center computers. CXL is built on the serial PCI Express (PCIe) physical |
| 72 | + and electrical interface and includes PCIe-based block input/output protocol |
| 73 | + (CXL.io), cache-coherent protocols for accessing system memory (CXL.cache), |
| 74 | + and device memory (CXL.mem). |
| 75 | + |
| 76 | +oneAPI Threading Building Blocks (oneTBB_) |
| 77 | + A C++ template library developed by Intel for parallel programming on |
| 78 | + multi-core processors. TBB broke down the computation into tasks that can run |
| 79 | + in parallel. The library manages and schedules threads to execute these tasks. |
| 80 | + |
| 81 | +jemalloc |
| 82 | + A general-purpose malloc implementation that emphasizes fragmentation |
| 83 | + avoidance and scalable concurrency support. It provides introspection, memory |
| 84 | + management, and tuning features functionalities. Jemalloc_ uses separate pools |
| 85 | + (“arenas”) for each CPU which avoids lock contention problems in |
| 86 | + multithreading applications and makes them scale linearly with the number of |
| 87 | + threads. |
| 88 | + |
| 89 | +Unified Shared Memory (USM) |
| 90 | + A programming model which provides a single memory address space that is |
| 91 | + shared between CPUs, GPUs, and possibly other accelerators. It simplifies |
| 92 | + memory management by transparently handling data migration between the CPU |
| 93 | + and the accelerator device as needed. |
| 94 | + |
| 95 | +.. _CXL https://www.computeexpresslink.org/ |
| 96 | +.. _oneTBB https://oneapi-src.github.io/oneTBB/ |
| 97 | +.. _Jemalloc https://jemalloc.net/ |
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