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[RISC][GISel] Consider ABI copies when picking register bank for G_LOAD/STORE.
This is partially based on AArch64, but reduced to handle just the case we currently have a test for.
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3 files changed

+48
-39
lines changed

3 files changed

+48
-39
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 22 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,9 @@ static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
110110
}
111111

112112
// TODO: Make this more like AArch64?
113-
static bool onlyUsesFP(const MachineInstr &MI) {
113+
bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
114+
const MachineRegisterInfo &MRI,
115+
const TargetRegisterInfo &TRI) const {
114116
switch (MI.getOpcode()) {
115117
case TargetOpcode::G_FADD:
116118
case TargetOpcode::G_FSUB:
@@ -131,11 +133,19 @@ static bool onlyUsesFP(const MachineInstr &MI) {
131133
break;
132134
}
133135

136+
// If we have a copy instruction, we could be feeding floating point
137+
// instructions.
138+
if (MI.getOpcode() == TargetOpcode::COPY)
139+
return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
140+
&RISCV::FPRBRegBank;
141+
134142
return false;
135143
}
136144

137145
// TODO: Make this more like AArch64?
138-
static bool onlyDefinesFP(const MachineInstr &MI) {
146+
bool RISCVRegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
147+
const MachineRegisterInfo &MRI,
148+
const TargetRegisterInfo &TRI) const {
139149
switch (MI.getOpcode()) {
140150
case TargetOpcode::G_FADD:
141151
case TargetOpcode::G_FSUB:
@@ -156,6 +166,12 @@ static bool onlyDefinesFP(const MachineInstr &MI) {
156166
break;
157167
}
158168

169+
// If we have a copy instruction, we could be fed by floating point
170+
// instructions.
171+
if (MI.getOpcode() == TargetOpcode::COPY)
172+
return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
173+
&RISCV::FPRBRegBank;
174+
159175
return false;
160176
}
161177

@@ -173,6 +189,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
173189

174190
const MachineFunction &MF = *MI.getParent()->getParent();
175191
const MachineRegisterInfo &MRI = MF.getRegInfo();
192+
const TargetSubtargetInfo &STI = MF.getSubtarget();
193+
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
176194

177195
unsigned GPRSize = getMaximumSize(RISCV::GPRBRegBankID);
178196
assert((GPRSize == 32 || GPRSize == 64) && "Unexpected GPR size");
@@ -235,7 +253,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
235253
// assume this was a floating point load in the IR. If it was
236254
// not, we would have had a bitcast before reaching that
237255
// instruction.
238-
return onlyUsesFP(UseMI);
256+
return onlyUsesFP(UseMI, MRI, TRI);
239257
})) {
240258
OperandsMapping = getOperandsMapping(
241259
{getFPValueMapping(Ty.getSizeInBits()), GPRValueMapping});
@@ -254,7 +272,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
254272
}
255273

256274
MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
257-
if (onlyDefinesFP(*DefMI)) {
275+
if (onlyDefinesFP(*DefMI, MRI, TRI)) {
258276
OperandsMapping = getOperandsMapping(
259277
{getFPValueMapping(Ty.getSizeInBits()), GPRValueMapping});
260278
}

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,15 @@ class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {
3838

3939
const InstructionMapping &
4040
getInstrMapping(const MachineInstr &MI) const override;
41+
42+
private:
43+
/// \returns true if \p MI only uses FPRs.
44+
bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
45+
const TargetRegisterInfo &TRI) const;
46+
47+
/// \returns true if \p MI only defines FPRs.
48+
bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
49+
const TargetRegisterInfo &TRI) const;
4150
};
4251
} // end namespace llvm
4352
#endif

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir

Lines changed: 17 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
33
# RUN: -simplify-mir -verify-machineinstrs %s \
4-
# RUN: -o - | FileCheck %s --check-prefixes=CHECK,RV32
4+
# RUN: -o - | FileCheck %s --check-prefixes=CHECK
55
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
66
# RUN: -simplify-mir -verify-machineinstrs %s \
7-
# RUN: -o - | FileCheck %s --check-prefixes=CHECK,RV64
7+
# RUN: -o - | FileCheck %s --check-prefixes=CHECK
88

99
---
1010
name: fp_store_fp_def_f32
@@ -64,22 +64,13 @@ body: |
6464
bb.1:
6565
liveins: $x10, $f10_d
6666
67-
; RV32-LABEL: name: fp_store_no_def_f64
68-
; RV32: liveins: $x10, $f10_d
69-
; RV32-NEXT: {{ $}}
70-
; RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
71-
; RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
72-
; RV32-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
73-
; RV32-NEXT: PseudoRET
74-
;
75-
; RV64-LABEL: name: fp_store_no_def_f64
76-
; RV64: liveins: $x10, $f10_d
77-
; RV64-NEXT: {{ $}}
78-
; RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
79-
; RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
80-
; RV64-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY [[COPY1]](s64)
81-
; RV64-NEXT: G_STORE [[COPY2]](s64), [[COPY]](p0) :: (store (s64))
82-
; RV64-NEXT: PseudoRET
67+
; CHECK-LABEL: name: fp_store_no_def_f64
68+
; CHECK: liveins: $x10, $f10_d
69+
; CHECK-NEXT: {{ $}}
70+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
71+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
72+
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
73+
; CHECK-NEXT: PseudoRET
8374
%0:_(p0) = COPY $x10
8475
%1:_(s64) = COPY $f10_d
8576
G_STORE %1(s64), %0(p0) :: (store (s64))
@@ -144,23 +135,14 @@ body: |
144135
bb.1:
145136
liveins: $x10, $f10_d
146137
147-
; RV32-LABEL: name: fp_load_no_use_f64
148-
; RV32: liveins: $x10, $f10_d
149-
; RV32-NEXT: {{ $}}
150-
; RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
151-
; RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
152-
; RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
153-
; RV32-NEXT: $f10_d = COPY [[LOAD]](s64)
154-
; RV32-NEXT: PseudoRET implicit $f10_d
155-
;
156-
; RV64-LABEL: name: fp_load_no_use_f64
157-
; RV64: liveins: $x10, $f10_d
158-
; RV64-NEXT: {{ $}}
159-
; RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
160-
; RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
161-
; RV64-NEXT: [[LOAD:%[0-9]+]]:gprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
162-
; RV64-NEXT: $f10_d = COPY [[LOAD]](s64)
163-
; RV64-NEXT: PseudoRET implicit $f10_d
138+
; CHECK-LABEL: name: fp_load_no_use_f64
139+
; CHECK: liveins: $x10, $f10_d
140+
; CHECK-NEXT: {{ $}}
141+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
142+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
143+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
144+
; CHECK-NEXT: $f10_d = COPY [[LOAD]](s64)
145+
; CHECK-NEXT: PseudoRET implicit $f10_d
164146
%0:_(p0) = COPY $x10
165147
%1:_(s64) = COPY $f10_d
166148
%2:_(s64) = G_LOAD %0(p0) :: (load (s64))

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