[RISCV] Implement Xcvelw Intrinsics

Implement Xcvelw CodeGen intrinsics.

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

Author: realqhc

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -1768,4 +1768,7 @@ def int_riscv_cv_mac_macurn   : ScalarCoreVMacGprGprGprImmIntrinsic;
 def int_riscv_cv_mac_machhurn : ScalarCoreVMacGprGprGprImmIntrinsic;
 def int_riscv_cv_mac_macsrn   : ScalarCoreVMacGprGprGprImmIntrinsic;
 def int_riscv_cv_mac_machhsrn : ScalarCoreVMacGprGprGprImmIntrinsic;
+
+def int_riscv_cv_elw_elw
+  : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
 } // TargetPrefix = "riscv"

llvm/lib/Support/RISCVISAInfo.cpp

@@ -107,7 +107,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
     {"xcvsimd", RISCVExtensionVersion{1, 0}},
     {"xcvbitmanip", RISCVExtensionVersion{1, 0}},
     {"xcvbi", RISCVExtensionVersion{1, 0}},
-    {"xcvmac", RISCVExtensionVersion{1, 0}}
+    {"xcvmac", RISCVExtensionVersion{1, 0}},
+    {"xcvelw", RISCVExtensionVersion{1, 0}}
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -2800,6 +2800,9 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
   case RISCV::PseudoFSD:
     emitLoadStoreSymbol(Inst, RISCV::FSD, IDLoc, Out, /*HasTmpReg=*/true);
     return false;
+  case RISCV::PseudoCV_ELW:
+    emitLoadStoreSymbol(Inst, RISCV::CV_ELW, IDLoc, Out, /*HasTmpReg=*/true);
+    return false;
   case RISCV::PseudoAddTPRel:
     if (checkPseudoAddTPRel(Inst, Operands))
       return true;

llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td

@@ -629,6 +629,7 @@ let Predicates = [HasExtXcvbitmanip, IsRV32], hasSideEffects = 0, mayLoad = 0, m
 }
 
 let Predicates = [HasExtXcvelw], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+  def PseudoCV_ELW : PseudoLoad<"cv.elw">;
   def CV_ELW : RVInstLoad_ri_inc<0b011, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
                                  "cv.elw", "$rd, ${imm12}(${rs1})", []>,
                Sched<[]>;
@@ -1136,6 +1137,12 @@ let Predicates = [HasExtXcvbitmanip, IsRV32] in {
             (CV_BITREV GPR:$rs1, cv_tuimm5:$pts, cv_tuimm2:$radix)>;
 }
 
+let Predicates = [HasExtXcvelw, IsRV32] in {
+  def : Pat<(int_riscv_cv_elw_elw GPR:$rs1), (PseudoCV_ELW GPR:$rs1)>;
+  def : Pat<(int_riscv_cv_elw_elw (AddrRegImm GPR:$rs1, simm12:$imm12)),
+            (CV_ELW GPR:$rs1, simm12:$imm12)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Pseudo instructions and patterns for hardware loop generation
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/corev/elw.ll

@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+xcvelw -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+declare i32 @llvm.riscv.cv.elw.elw(i8*)
+
+define i32 @test.cv.elw.elw(i8* %a) {
+; CHECK-LABEL: test.cv.elw.elw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.elw a0, 0(a0)
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.elw.elw(i8* %a)
+  ret i32 %1
+}
+
+define i32 @test.cv.elw.elw2(i8* %a, i32 %b) {
+; CHECK-LABEL: test.cv.elw.elw2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add a0, a1, a0
+; CHECK-NEXT:    cv.elw a0, 7(a0)
+; CHECK-NEXT:    ret
+  %c = add i32 %b, 4
+  %d = add i32 %c, 3
+  %e = getelementptr i8, i8* %a, i32 %d
+  %1 = call i32 @llvm.riscv.cv.elw.elw(i8* %e)
+  ret i32 %1
+}