@@ -5752,6 +5752,7 @@ static struct intel_uncore_type spr_uncore_mdf = {
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};
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#define UNCORE_SPR_NUM_UNCORE_TYPES 12
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+ #define UNCORE_SPR_IIO 1
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static struct intel_uncore_type * spr_uncores [UNCORE_SPR_NUM_UNCORE_TYPES ] = {
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& spr_uncore_chabox ,
@@ -5768,6 +5769,92 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
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& spr_uncore_mdf ,
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};
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+ enum perf_uncore_spr_iio_freerunning_type_id {
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+ SPR_IIO_MSR_IOCLK ,
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+ SPR_IIO_MSR_BW_IN ,
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+ SPR_IIO_MSR_BW_OUT ,
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+
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+ SPR_IIO_FREERUNNING_TYPE_MAX ,
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+ };
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+
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+ static struct freerunning_counters spr_iio_freerunning [] = {
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+ [SPR_IIO_MSR_IOCLK ] = { 0x340e , 0x1 , 0x10 , 1 , 48 },
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+ [SPR_IIO_MSR_BW_IN ] = { 0x3800 , 0x1 , 0x10 , 8 , 48 },
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+ [SPR_IIO_MSR_BW_OUT ] = { 0x3808 , 0x1 , 0x10 , 8 , 48 },
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+ };
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+
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+ static struct uncore_event_desc spr_uncore_iio_freerunning_events [] = {
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+ /* Free-Running IIO CLOCKS Counter */
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+ INTEL_UNCORE_EVENT_DESC (ioclk , "event=0xff,umask=0x10" ),
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+ /* Free-Running IIO BANDWIDTH IN Counters */
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port0 , "event=0xff,umask=0x20" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port0 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port0 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port1 , "event=0xff,umask=0x21" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port1 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port1 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port2 , "event=0xff,umask=0x22" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port2 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port2 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port3 , "event=0xff,umask=0x23" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port3 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port3 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port4 , "event=0xff,umask=0x24" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port4 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port4 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port5 , "event=0xff,umask=0x25" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port5 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port5 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port6 , "event=0xff,umask=0x26" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port6 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port6 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port7 , "event=0xff,umask=0x27" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port7 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_in_port7 .unit , "MiB" ),
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+ /* Free-Running IIO BANDWIDTH OUT Counters */
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port0 , "event=0xff,umask=0x30" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port0 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port0 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port1 , "event=0xff,umask=0x31" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port1 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port1 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port2 , "event=0xff,umask=0x32" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port2 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port2 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port3 , "event=0xff,umask=0x33" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port3 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port3 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port4 , "event=0xff,umask=0x34" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port4 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port4 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port5 , "event=0xff,umask=0x35" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port5 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port5 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port6 , "event=0xff,umask=0x36" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port6 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port6 .unit , "MiB" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port7 , "event=0xff,umask=0x37" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port7 .scale , "3.814697266e-6" ),
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+ INTEL_UNCORE_EVENT_DESC (bw_out_port7 .unit , "MiB" ),
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+ { /* end: all zeroes */ },
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+ };
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+
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+ static struct intel_uncore_type spr_uncore_iio_free_running = {
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+ .name = "iio_free_running" ,
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+ .num_counters = 17 ,
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+ .num_freerunning_types = SPR_IIO_FREERUNNING_TYPE_MAX ,
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+ .freerunning = spr_iio_freerunning ,
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+ .ops = & skx_uncore_iio_freerunning_ops ,
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+ .event_descs = spr_uncore_iio_freerunning_events ,
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+ .format_group = & skx_uncore_iio_freerunning_format_group ,
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+ };
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+
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+ #define UNCORE_SPR_MSR_EXTRA_UNCORES 1
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+
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+ static struct intel_uncore_type * spr_msr_uncores [UNCORE_SPR_MSR_EXTRA_UNCORES ] = {
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+ & spr_uncore_iio_free_running ,
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+ };
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+
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static void uncore_type_customized_copy (struct intel_uncore_type * to_type ,
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struct intel_uncore_type * from_type )
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{
@@ -5803,11 +5890,13 @@ static void uncore_type_customized_copy(struct intel_uncore_type *to_type,
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}
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static struct intel_uncore_type * *
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- uncore_get_uncores (enum uncore_access_type type_id )
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+ uncore_get_uncores (enum uncore_access_type type_id , int num_extra ,
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+ struct intel_uncore_type * * extra )
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{
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struct intel_uncore_type * * types , * * start_types ;
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+ int i ;
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- start_types = types = intel_uncore_generic_init_uncores (type_id );
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+ start_types = types = intel_uncore_generic_init_uncores (type_id , num_extra );
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/* Only copy the customized features */
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for (; * types ; types ++ ) {
@@ -5816,23 +5905,59 @@ uncore_get_uncores(enum uncore_access_type type_id)
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uncore_type_customized_copy (* types , spr_uncores [(* types )-> type_id ]);
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}
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+ for (i = 0 ; i < num_extra ; i ++ , types ++ )
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+ * types = extra [i ];
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+
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return start_types ;
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}
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+ static struct intel_uncore_type *
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+ uncore_find_type_by_id (struct intel_uncore_type * * types , int type_id )
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+ {
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+ for (; * types ; types ++ ) {
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+ if (type_id == (* types )-> type_id )
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+ return * types ;
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+ }
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+
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+ return NULL ;
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+ }
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+
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+ static int uncore_type_max_boxes (struct intel_uncore_type * * types ,
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+ int type_id )
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+ {
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+ struct intel_uncore_type * type ;
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+ int i , max = 0 ;
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+
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+ type = uncore_find_type_by_id (types , type_id );
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+ if (!type )
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+ return 0 ;
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+
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+ for (i = 0 ; i < type -> num_boxes ; i ++ ) {
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+ if (type -> box_ids [i ] > max )
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+ max = type -> box_ids [i ];
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+ }
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+
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+ return max + 1 ;
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+ }
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+
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void spr_uncore_cpu_init (void )
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{
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- uncore_msr_uncores = uncore_get_uncores (UNCORE_ACCESS_MSR );
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+ uncore_msr_uncores = uncore_get_uncores (UNCORE_ACCESS_MSR ,
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+ UNCORE_SPR_MSR_EXTRA_UNCORES ,
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+ spr_msr_uncores );
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+
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+ spr_uncore_iio_free_running .num_boxes = uncore_type_max_boxes (uncore_msr_uncores , UNCORE_SPR_IIO );
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}
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int spr_uncore_pci_init (void )
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{
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- uncore_pci_uncores = uncore_get_uncores (UNCORE_ACCESS_PCI );
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+ uncore_pci_uncores = uncore_get_uncores (UNCORE_ACCESS_PCI , 0 , NULL );
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return 0 ;
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}
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void spr_uncore_mmio_init (void )
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{
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- uncore_mmio_uncores = uncore_get_uncores (UNCORE_ACCESS_MMIO );
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+ uncore_mmio_uncores = uncore_get_uncores (UNCORE_ACCESS_MMIO , 0 , NULL );
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}
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/* end of SPR uncore support */
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