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whitebrandybonzini
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nVMX: Advertise PML to L1 hypervisor
Advertise the PML bit in vmcs12 but don't try to enable it in hardware when running L2 since L0 is emulating it. Also, preserve L0's settings for PML since it may still want to log writes. Signed-off-by: Bandan Das <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
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arch/x86/kvm/vmx.c

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2766,8 +2766,11 @@ static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
27662766
vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
27672767
VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
27682768
VMX_EPT_1GB_PAGE_BIT;
2769-
if (enable_ept_ad_bits)
2769+
if (enable_ept_ad_bits) {
2770+
vmx->nested.nested_vmx_secondary_ctls_high |=
2771+
SECONDARY_EXEC_ENABLE_PML;
27702772
vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2773+
}
27712774
} else
27722775
vmx->nested.nested_vmx_ept_caps = 0;
27732776

@@ -8129,7 +8132,7 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
81298132
case EXIT_REASON_PREEMPTION_TIMER:
81308133
return false;
81318134
case EXIT_REASON_PML_FULL:
8132-
/* We don't expose PML support to L1. */
8135+
/* We emulate PML support to L1. */
81338136
return false;
81348137
default:
81358138
return true;
@@ -9924,7 +9927,7 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
99249927
bool from_vmentry, u32 *entry_failure_code)
99259928
{
99269929
struct vcpu_vmx *vmx = to_vmx(vcpu);
9927-
u32 exec_control;
9930+
u32 exec_control, vmcs12_exec_ctrl;
99289931

99299932
vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
99309933
vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
@@ -10055,8 +10058,11 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
1005510058
SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
1005610059
SECONDARY_EXEC_APIC_REGISTER_VIRT);
1005710060
if (nested_cpu_has(vmcs12,
10058-
CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10059-
exec_control |= vmcs12->secondary_vm_exec_control;
10061+
CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10062+
vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10063+
~SECONDARY_EXEC_ENABLE_PML;
10064+
exec_control |= vmcs12_exec_ctrl;
10065+
}
1006010066

1006110067
if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
1006210068
vmcs_write64(EOI_EXIT_BITMAP0,

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