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217 | 217 | >;
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218 | 218 | };
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219 | 219 |
|
| 220 | + isp_pins: pinmux_isp_pins { |
| 221 | + pinctrl-single,pins = < |
| 222 | + OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ |
| 223 | + OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ |
| 224 | + OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ |
| 225 | + OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ |
| 226 | + |
| 227 | + OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ |
| 228 | + OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ |
| 229 | + OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ |
| 230 | + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ |
| 231 | + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ |
| 232 | + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ |
| 233 | + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ |
| 234 | + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ |
| 235 | + >; |
| 236 | + }; |
| 237 | + |
220 | 238 | dss_dpi_pins1: pinmux_dss_dpi_pins1 {
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221 | 239 | pinctrl-single,pins = <
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222 | 240 | OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
|
|
268 | 286 | };
|
269 | 287 | };
|
270 | 288 |
|
| 289 | +&i2c2 { |
| 290 | + mt9p031@48 { |
| 291 | + compatible = "aptina,mt9p031"; |
| 292 | + reg = <0x48>; |
| 293 | + clocks = <&isp 0>; |
| 294 | + vaa-supply = <&vaux4>; |
| 295 | + vdd-supply = <&vaux4>; |
| 296 | + vdd_io-supply = <&vaux4>; |
| 297 | + port { |
| 298 | + mt9p031_out: endpoint { |
| 299 | + input-clock-frequency = <24000000>; |
| 300 | + pixel-clock-frequency = <72000000>; |
| 301 | + remote-endpoint = <&ccdc_ep>; |
| 302 | + }; |
| 303 | + }; |
| 304 | + }; |
| 305 | +}; |
| 306 | + |
271 | 307 | &i2c3 {
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272 | 308 | touchscreen: tsc2004@48 {
|
273 | 309 | compatible = "ti,tsc2004";
|
|
289 | 325 | };
|
290 | 326 | };
|
291 | 327 |
|
| 328 | +&isp { |
| 329 | + pinctrl-names = "default"; |
| 330 | + pinctrl-0 = <&isp_pins>; |
| 331 | + ports { |
| 332 | + port@0 { |
| 333 | + reg = <0>; |
| 334 | + ccdc_ep: endpoint { |
| 335 | + remote-endpoint = <&mt9p031_out>; |
| 336 | + bus-width = <8>; |
| 337 | + hsync-active = <1>; |
| 338 | + vsync-active = <1>; |
| 339 | + pclk-sample = <0>; |
| 340 | + }; |
| 341 | + }; |
| 342 | + }; |
| 343 | +}; |
| 344 | + |
292 | 345 | &uart1 {
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293 | 346 | interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
|
294 | 347 | };
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