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torvaldstorvalds
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Aome amdgpu, one i915, one ttm and one hlcdc, nothing too scary. All seems fine for about this time" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/ttm: recognize ARM64 arch in ioprot handler drm/amdgpu/cz/dpm: properly report UVD and VCE clock levels drm/amdgpu/cz: implement voltage validation properly drm/amdgpu: add VCE harvesting instance query drm/amdgpu: implement VCE 3.0 harvesting support (v4) drm/amdgpu/dce10: Re-set VBLANK interrupt state when enabling a CRTC drm/amdgpu/dce11: Re-set VBLANK interrupt state when enabling a CRTC drm: Stop resetting connector state to unknown drm/i915: Use two 32bit reads for select 64bit REG_READ ioctls drm: atmel-hlcdc: fix vblank initial state
2 parents b497500 + 02bbc4d commit 077b205

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13 files changed

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-34
lines changed

13 files changed

+154
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lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1614,6 +1614,9 @@ struct amdgpu_uvd {
16141614
#define AMDGPU_MAX_VCE_HANDLES 16
16151615
#define AMDGPU_VCE_FIRMWARE_OFFSET 256
16161616

1617+
#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1618+
#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1619+
16171620
struct amdgpu_vce {
16181621
struct amdgpu_bo *vcpu_bo;
16191622
uint64_t gpu_addr;
@@ -1626,6 +1629,7 @@ struct amdgpu_vce {
16261629
const struct firmware *fw; /* VCE firmware */
16271630
struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
16281631
struct amdgpu_irq_src irq;
1632+
unsigned harvest_config;
16291633
};
16301634

16311635
/*

‎drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -459,6 +459,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
459459
memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
460460
dev_info.vram_type = adev->mc.vram_type;
461461
dev_info.vram_bit_width = adev->mc.vram_width;
462+
dev_info.vce_harvest_config = adev->vce.harvest_config;
462463

463464
return copy_to_user(out, &dev_info,
464465
min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;

‎drivers/gpu/drm/amd/amdgpu/cz_dpm.c

Lines changed: 54 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -494,29 +494,67 @@ static void cz_dpm_fini(struct amdgpu_device *adev)
494494
amdgpu_free_extended_power_table(adev);
495495
}
496496

497+
#define ixSMUSVI_NB_CURRENTVID 0xD8230044
498+
#define CURRENT_NB_VID_MASK 0xff000000
499+
#define CURRENT_NB_VID__SHIFT 24
500+
#define ixSMUSVI_GFX_CURRENTVID 0xD8230048
501+
#define CURRENT_GFX_VID_MASK 0xff000000
502+
#define CURRENT_GFX_VID__SHIFT 24
503+
497504
static void
498505
cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
499506
struct seq_file *m)
500507
{
508+
struct cz_power_info *pi = cz_get_pi(adev);
501509
struct amdgpu_clock_voltage_dependency_table *table =
502510
&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
503-
u32 current_index =
504-
(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
505-
TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
506-
TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
507-
u32 sclk, tmp;
508-
u16 vddc;
509-
510-
if (current_index >= NUM_SCLK_LEVELS) {
511-
seq_printf(m, "invalid dpm profile %d\n", current_index);
511+
struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
512+
&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
513+
struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
514+
&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
515+
u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
516+
TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
517+
u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
518+
TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
519+
u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
520+
TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
521+
u32 sclk, vclk, dclk, ecclk, tmp;
522+
u16 vddnb, vddgfx;
523+
524+
if (sclk_index >= NUM_SCLK_LEVELS) {
525+
seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
512526
} else {
513-
sclk = table->entries[current_index].clk;
514-
tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
515-
SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
516-
SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
517-
vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
518-
seq_printf(m, "power level %d sclk: %u vddc: %u\n",
519-
current_index, sclk, vddc);
527+
sclk = table->entries[sclk_index].clk;
528+
seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
529+
}
530+
531+
tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
532+
CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
533+
vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
534+
tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
535+
CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
536+
vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
537+
seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
538+
539+
seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
540+
if (!pi->uvd_power_gated) {
541+
if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
542+
seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
543+
} else {
544+
vclk = uvd_table->entries[uvd_index].vclk;
545+
dclk = uvd_table->entries[uvd_index].dclk;
546+
seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
547+
}
548+
}
549+
550+
seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
551+
if (!pi->vce_power_gated) {
552+
if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
553+
seq_printf(m, "invalid vce dpm level %d\n", vce_index);
554+
} else {
555+
ecclk = vce_table->entries[vce_index].ecclk;
556+
seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
557+
}
520558
}
521559
}
522560

‎drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2632,6 +2632,7 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
26322632
struct drm_device *dev = crtc->dev;
26332633
struct amdgpu_device *adev = dev->dev_private;
26342634
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2635+
unsigned type;
26352636

26362637
switch (mode) {
26372638
case DRM_MODE_DPMS_ON:
@@ -2640,6 +2641,9 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
26402641
dce_v10_0_vga_enable(crtc, true);
26412642
amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
26422643
dce_v10_0_vga_enable(crtc, false);
2644+
/* Make sure VBLANK interrupt is still enabled */
2645+
type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2646+
amdgpu_irq_update(adev, &adev->crtc_irq, type);
26432647
drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
26442648
dce_v10_0_crtc_load_lut(crtc);
26452649
break;

‎drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2631,6 +2631,7 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
26312631
struct drm_device *dev = crtc->dev;
26322632
struct amdgpu_device *adev = dev->dev_private;
26332633
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2634+
unsigned type;
26342635

26352636
switch (mode) {
26362637
case DRM_MODE_DPMS_ON:
@@ -2639,6 +2640,9 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
26392640
dce_v11_0_vga_enable(crtc, true);
26402641
amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
26412642
dce_v11_0_vga_enable(crtc, false);
2643+
/* Make sure VBLANK interrupt is still enabled */
2644+
type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2645+
amdgpu_irq_update(adev, &adev->crtc_irq, type);
26422646
drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
26432647
dce_v11_0_crtc_load_lut(crtc);
26442648
break;

‎drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,8 @@
3535
#include "oss/oss_2_0_d.h"
3636
#include "oss/oss_2_0_sh_mask.h"
3737
#include "gca/gfx_8_0_d.h"
38+
#include "smu/smu_7_1_2_d.h"
39+
#include "smu/smu_7_1_2_sh_mask.h"
3840

3941
#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
4042
#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
@@ -112,6 +114,10 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
112114

113115
mutex_lock(&adev->grbm_idx_mutex);
114116
for (idx = 0; idx < 2; ++idx) {
117+
118+
if (adev->vce.harvest_config & (1 << idx))
119+
continue;
120+
115121
if(idx == 0)
116122
WREG32_P(mmGRBM_GFX_INDEX, 0,
117123
~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
@@ -190,10 +196,52 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
190196
return 0;
191197
}
192198

199+
#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
200+
#define VCE_HARVEST_FUSE_MACRO__SHIFT 27
201+
#define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
202+
203+
static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
204+
{
205+
u32 tmp;
206+
unsigned ret;
207+
208+
if (adev->flags & AMDGPU_IS_APU)
209+
tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
210+
VCE_HARVEST_FUSE_MACRO__MASK) >>
211+
VCE_HARVEST_FUSE_MACRO__SHIFT;
212+
else
213+
tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
214+
CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
215+
CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
216+
217+
switch (tmp) {
218+
case 1:
219+
ret = AMDGPU_VCE_HARVEST_VCE0;
220+
break;
221+
case 2:
222+
ret = AMDGPU_VCE_HARVEST_VCE1;
223+
break;
224+
case 3:
225+
ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
226+
break;
227+
default:
228+
ret = 0;
229+
}
230+
231+
return ret;
232+
}
233+
193234
static int vce_v3_0_early_init(void *handle)
194235
{
195236
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
196237

238+
adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
239+
240+
if ((adev->vce.harvest_config &
241+
(AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) ==
242+
(AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
243+
return -ENOENT;
244+
197245
vce_v3_0_set_ring_funcs(adev);
198246
vce_v3_0_set_irq_funcs(adev);
199247

‎drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -355,6 +355,7 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev)
355355
planes->overlays[i]->base.possible_crtcs = 1 << crtc->id;
356356

357357
drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
358+
drm_crtc_vblank_reset(&crtc->base);
358359

359360
dc->crtc = &crtc->base;
360361

‎drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -313,20 +313,20 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev)
313313

314314
pm_runtime_enable(dev->dev);
315315

316-
ret = atmel_hlcdc_dc_modeset_init(dev);
316+
ret = drm_vblank_init(dev, 1);
317317
if (ret < 0) {
318-
dev_err(dev->dev, "failed to initialize mode setting\n");
318+
dev_err(dev->dev, "failed to initialize vblank\n");
319319
goto err_periph_clk_disable;
320320
}
321321

322-
drm_mode_config_reset(dev);
323-
324-
ret = drm_vblank_init(dev, 1);
322+
ret = atmel_hlcdc_dc_modeset_init(dev);
325323
if (ret < 0) {
326-
dev_err(dev->dev, "failed to initialize vblank\n");
324+
dev_err(dev->dev, "failed to initialize mode setting\n");
327325
goto err_periph_clk_disable;
328326
}
329327

328+
drm_mode_config_reset(dev);
329+
330330
pm_runtime_get_sync(dev->dev);
331331
ret = drm_irq_install(dev, dc->hlcdc->irq);
332332
pm_runtime_put_sync(dev->dev);

‎drivers/gpu/drm/drm_crtc.c

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5398,12 +5398,9 @@ void drm_mode_config_reset(struct drm_device *dev)
53985398
if (encoder->funcs->reset)
53995399
encoder->funcs->reset(encoder);
54005400

5401-
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5402-
connector->status = connector_status_unknown;
5403-
5401+
list_for_each_entry(connector, &dev->mode_config.connector_list, head)
54045402
if (connector->funcs->reset)
54055403
connector->funcs->reset(connector);
5406-
}
54075404
}
54085405
EXPORT_SYMBOL(drm_mode_config_reset);
54095406

‎drivers/gpu/drm/i915/intel_uncore.c

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1274,34 +1274,46 @@ int i915_reg_read_ioctl(struct drm_device *dev,
12741274
struct drm_i915_private *dev_priv = dev->dev_private;
12751275
struct drm_i915_reg_read *reg = data;
12761276
struct register_whitelist const *entry = whitelist;
1277+
unsigned size;
1278+
u64 offset;
12771279
int i, ret = 0;
12781280

12791281
for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1280-
if (entry->offset == reg->offset &&
1282+
if (entry->offset == (reg->offset & -entry->size) &&
12811283
(1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
12821284
break;
12831285
}
12841286

12851287
if (i == ARRAY_SIZE(whitelist))
12861288
return -EINVAL;
12871289

1290+
/* We use the low bits to encode extra flags as the register should
1291+
* be naturally aligned (and those that are not so aligned merely
1292+
* limit the available flags for that register).
1293+
*/
1294+
offset = entry->offset;
1295+
size = entry->size;
1296+
size |= reg->offset ^ offset;
1297+
12881298
intel_runtime_pm_get(dev_priv);
12891299

1290-
switch (entry->size) {
1300+
switch (size) {
1301+
case 8 | 1:
1302+
reg->val = I915_READ64_2x32(offset, offset+4);
1303+
break;
12911304
case 8:
1292-
reg->val = I915_READ64(reg->offset);
1305+
reg->val = I915_READ64(offset);
12931306
break;
12941307
case 4:
1295-
reg->val = I915_READ(reg->offset);
1308+
reg->val = I915_READ(offset);
12961309
break;
12971310
case 2:
1298-
reg->val = I915_READ16(reg->offset);
1311+
reg->val = I915_READ16(offset);
12991312
break;
13001313
case 1:
1301-
reg->val = I915_READ8(reg->offset);
1314+
reg->val = I915_READ8(offset);
13021315
break;
13031316
default:
1304-
MISSING_CASE(entry->size);
13051317
ret = -EINVAL;
13061318
goto out;
13071319
}

‎drivers/gpu/drm/ttm/ttm_bo_util.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -490,7 +490,8 @@ pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp)
490490
else if (boot_cpu_data.x86 > 3)
491491
tmp = pgprot_noncached(tmp);
492492
#endif
493-
#if defined(__ia64__) || defined(__arm__) || defined(__powerpc__)
493+
#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
494+
defined(__powerpc__)
494495
if (caching_flags & TTM_PL_FLAG_WC)
495496
tmp = pgprot_writecombine(tmp);
496497
else

‎include/uapi/drm/amdgpu_drm.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -614,6 +614,8 @@ struct drm_amdgpu_info_device {
614614
uint32_t vram_type;
615615
/** video memory bit width*/
616616
uint32_t vram_bit_width;
617+
/* vce harvesting instance */
618+
uint32_t vce_harvest_config;
617619
};
618620

619621
struct drm_amdgpu_info_hw_ip {

‎include/uapi/drm/i915_drm.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1070,6 +1070,14 @@ struct drm_i915_reg_read {
10701070
__u64 offset;
10711071
__u64 val; /* Return value */
10721072
};
1073+
/* Known registers:
1074+
*
1075+
* Render engine timestamp - 0x2358 + 64bit - gen7+
1076+
* - Note this register returns an invalid value if using the default
1077+
* single instruction 8byte read, in order to workaround that use
1078+
* offset (0x2538 | 1) instead.
1079+
*
1080+
*/
10731081

10741082
struct drm_i915_reset_stats {
10751083
__u32 ctx_id;

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