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#define NVMEM_MASK 0x7
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#define NVMEM_SHIFT 5
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+ #define SUN50I_A100_NVMEM_MASK 0xf
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+ #define SUN50I_A100_NVMEM_SHIFT 12
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+
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static struct platform_device * cpufreq_dt_pdev , * sun50i_cpufreq_pdev ;
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struct sunxi_cpufreq_data {
@@ -45,6 +48,23 @@ static u32 sun50i_h6_efuse_xlate(u32 speedbin)
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return 0 ;
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}
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+ static u32 sun50i_a100_efuse_xlate (u32 speedbin )
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+ {
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+ u32 efuse_value ;
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+
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+ efuse_value = (speedbin >> SUN50I_A100_NVMEM_SHIFT ) &
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+ SUN50I_A100_NVMEM_MASK ;
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+
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+ switch (efuse_value ) {
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+ case 0b100 :
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+ return 2 ;
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+ case 0b010 :
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+ return 1 ;
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+ default :
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+ return 0 ;
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+ }
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+ }
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+
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static int get_soc_id_revision (void )
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{
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#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
@@ -108,6 +128,10 @@ static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
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.efuse_xlate = sun50i_h6_efuse_xlate ,
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};
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+ static struct sunxi_cpufreq_data sun50i_a100_cpufreq_data = {
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+ .efuse_xlate = sun50i_a100_efuse_xlate ,
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+ };
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+
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static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
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.efuse_xlate = sun50i_h616_efuse_xlate ,
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};
@@ -116,6 +140,9 @@ static const struct of_device_id cpu_opp_match_list[] = {
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{ .compatible = "allwinner,sun50i-h6-operating-points" ,
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.data = & sun50i_h6_cpufreq_data ,
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},
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+ { .compatible = "allwinner,sun50i-a100-operating-points" ,
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+ .data = & sun50i_a100_cpufreq_data ,
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+ },
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{ .compatible = "allwinner,sun50i-h616-operating-points" ,
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.data = & sun50i_h616_cpufreq_data ,
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},
@@ -291,6 +318,7 @@ static struct platform_driver sun50i_cpufreq_driver = {
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static const struct of_device_id sun50i_cpufreq_match_list [] = {
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{ .compatible = "allwinner,sun50i-h6" },
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+ { .compatible = "allwinner,sun50i-a100" },
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{ .compatible = "allwinner,sun50i-h616" },
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{ .compatible = "allwinner,sun50i-h618" },
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{ .compatible = "allwinner,sun50i-h700" },
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