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Andre-ARMbebarino
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clk: sunxi-ng: h616: Reparent CPU clock during frequency changes
The H616 user manual recommends to re-parent the CPU clock during frequency changes of the PLL, and recommends PLL_PERI0(1X), which runs at 600 MHz. Also it asks to disable and then re-enable the PLL lock bit, after the factor changes have been applied. Add clock notifiers for the PLL and the CPU mux clock, using the existing notifier callbacks, and tell them to use mux 4 (the PLL_PERI0(1X) source), and bit 29 (the LOCK_ENABLE) bit. The existing code already follows the correct algorithms. Signed-off-by: Andre Przywara <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Evgeny Boger <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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drivers/clk/sunxi-ng/ccu-sun50i-h616.c

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1107,11 +1107,24 @@ static const u32 usb2_clk_regs[] = {
11071107
SUN50I_H616_USB3_CLK_REG,
11081108
};
11091109

1110+
static struct ccu_mux_nb sun50i_h616_cpu_nb = {
1111+
.common = &cpux_clk.common,
1112+
.cm = &cpux_clk.mux,
1113+
.delay_us = 1, /* manual doesn't really say */
1114+
.bypass_index = 4, /* PLL_PERI0@600MHz, as recommended by manual */
1115+
};
1116+
1117+
static struct ccu_pll_nb sun50i_h616_pll_cpu_nb = {
1118+
.common = &pll_cpux_clk.common,
1119+
.enable = BIT(29), /* LOCK_ENABLE */
1120+
.lock = BIT(28),
1121+
};
1122+
11101123
static int sun50i_h616_ccu_probe(struct platform_device *pdev)
11111124
{
11121125
void __iomem *reg;
11131126
u32 val;
1114-
int i;
1127+
int ret, i;
11151128

11161129
reg = devm_platform_ioremap_resource(pdev, 0);
11171130
if (IS_ERR(reg))
@@ -1166,7 +1179,18 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
11661179
val |= BIT(24);
11671180
writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG);
11681181

1169-
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);
1182+
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);
1183+
if (ret)
1184+
return ret;
1185+
1186+
/* Reparent CPU during CPU PLL rate changes */
1187+
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1188+
&sun50i_h616_cpu_nb);
1189+
1190+
/* Re-lock the CPU PLL after any rate changes */
1191+
ccu_pll_notifier_register(&sun50i_h616_pll_cpu_nb);
1192+
1193+
return 0;
11701194
}
11711195

11721196
static const struct of_device_id sun50i_h616_ccu_ids[] = {

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