ice: Fix quad registers read on E825

[ Upstream commit dc26548 ]

Quad registers are read/written incorrectly. E825 devices always use
quad 0 address and differentiate between the PHYs by changing SBQ
destination device (phy_0 or phy_0_peer).

Add helpers for reading/writing PTP registers shared per quad and use
correct quad address and SBQ destination device based on port.

Fixes: 7cab44f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Arkadiusz Kubalewski <[email protected]>
Signed-off-by: Karol Kolacinski <[email protected]>
Signed-off-by: Grzegorz Nitka <[email protected]>
Tested-by: Pucha Himasekhar Reddy <[email protected]> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>
(cherry picked from commit 0e5a802fcf5fe26f76edb7a5a502de01ee707204)
Signed-off-by: Jack Vogel <[email protected]>

Author: kolacinskikarol