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Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull clock controller fixes from Michael Turquette: "Two small fixes for the Zynq clock controller introduced in 3.11-rc1 and another Exynos clock patch which fixes a regression that prevents the video pipeline from functioning on that platform" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux: clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocks clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes clk/zynq/clkc: Add dedicated spinlock for the SWDT
2 parents 2d2843e + a701fe3 commit 0f7dd1a

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‎drivers/clk/samsung/clk-exynos4.c

Lines changed: 34 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -581,11 +581,15 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
581581
DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
582582
DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
583583
DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
584-
DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
585-
DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
584+
DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
585+
CLK_GET_RATE_NOCACHE, 0),
586+
DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
587+
CLK_GET_RATE_NOCACHE, 0),
586588
DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
587-
DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
588-
DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
589+
DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
590+
4, 3, CLK_GET_RATE_NOCACHE, 0),
591+
DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
592+
8, 3, CLK_GET_RATE_NOCACHE, 0),
589593
DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
590594
};
591595

@@ -863,57 +867,57 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
863867
GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
864868
E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
865869
GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
866-
CLK_IGNORE_UNUSED, 0),
870+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
867871
GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
868-
CLK_IGNORE_UNUSED, 0),
872+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
869873
GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
870-
CLK_IGNORE_UNUSED, 0),
874+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
871875
GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
872-
CLK_IGNORE_UNUSED, 0),
876+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
873877
GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
874-
CLK_IGNORE_UNUSED, 0),
878+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
875879
GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
876-
CLK_IGNORE_UNUSED, 0),
880+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
877881
GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
878-
CLK_IGNORE_UNUSED, 0),
882+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
879883
GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
880-
CLK_IGNORE_UNUSED, 0),
884+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
881885
GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
882-
CLK_IGNORE_UNUSED, 0),
886+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
883887
GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
884-
CLK_IGNORE_UNUSED, 0),
888+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
885889
GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
886-
CLK_IGNORE_UNUSED, 0),
890+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
887891
GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
888-
CLK_IGNORE_UNUSED, 0),
892+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
889893
GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
890-
CLK_IGNORE_UNUSED, 0),
894+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
891895
GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
892-
CLK_IGNORE_UNUSED, 0),
896+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
893897
GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
894-
CLK_IGNORE_UNUSED, 0),
898+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
895899
GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
896-
CLK_IGNORE_UNUSED, 0),
900+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
897901
GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
898-
CLK_IGNORE_UNUSED, 0),
902+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
899903
GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
900-
CLK_IGNORE_UNUSED, 0),
904+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
901905
GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
902-
CLK_IGNORE_UNUSED, 0),
906+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
903907
GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
904-
CLK_IGNORE_UNUSED, 0),
908+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
905909
GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
906-
CLK_IGNORE_UNUSED, 0),
910+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
907911
GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
908-
CLK_IGNORE_UNUSED, 0),
912+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
909913
GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
910-
CLK_IGNORE_UNUSED, 0),
914+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
911915
GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
912-
CLK_IGNORE_UNUSED, 0),
916+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
913917
GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
914-
CLK_IGNORE_UNUSED, 0),
918+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
915919
GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
916-
CLK_IGNORE_UNUSED, 0),
920+
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
917921
GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
918922
};
919923

‎drivers/clk/zynq/clkc.c

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(armpll_lock);
7171
static DEFINE_SPINLOCK(ddrpll_lock);
7272
static DEFINE_SPINLOCK(iopll_lock);
7373
static DEFINE_SPINLOCK(armclk_lock);
74+
static DEFINE_SPINLOCK(swdtclk_lock);
7475
static DEFINE_SPINLOCK(ddrclk_lock);
7576
static DEFINE_SPINLOCK(dciclk_lock);
7677
static DEFINE_SPINLOCK(gem0clk_lock);
@@ -293,7 +294,7 @@ static void __init zynq_clk_setup(struct device_node *np)
293294
}
294295
clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
295296
swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
296-
SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock);
297+
SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock);
297298

298299
/* DDR clocks */
299300
clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
@@ -364,8 +365,9 @@ static void __init zynq_clk_setup(struct device_node *np)
364365
CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
365366
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
366367
&gem0clk_lock);
367-
clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0,
368-
SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
368+
clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
369+
CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
370+
&gem0clk_lock);
369371
clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
370372
"gem0_emio_mux", CLK_SET_RATE_PARENT,
371373
SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
@@ -386,8 +388,9 @@ static void __init zynq_clk_setup(struct device_node *np)
386388
CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
387389
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
388390
&gem1clk_lock);
389-
clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0,
390-
SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
391+
clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
392+
CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
393+
&gem1clk_lock);
391394
clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
392395
"gem1_emio_mux", CLK_SET_RATE_PARENT,
393396
SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);

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