Skip to content

Commit 10f84de

Browse files
committed
Merge tag 'qcom-clk-fixes-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes
Pull Qualcomm clk driver fixes from Bjorn Andersson: - Correct the Stromer Plus PLL set_rate to explicitly set ALPHA_EN bit and remove unnecessary upper parts of CONFIG_CTL values. - Mark the recently added IPQ9574 GCC crypto clocks BRANCH_HALT_VOTED, to address stuck clock warnings. - Fix the GPLL6 and GPLL7 parents on SM6350 to avoid issues with these reportedly running at ~25GHz. * tag 'qcom-clk-fixes-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: gcc-ipq9574: Add BRANCH_HALT_VOTED flag clk: qcom: apss-ipq-pll: remove 'config_ctl_hi_val' from Stromer pll configs clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents
2 parents 878e845 + 72ceafb commit 10f84de

File tree

4 files changed

+14
-11
lines changed

4 files changed

+14
-11
lines changed

drivers/clk/qcom/apss-ipq-pll.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,6 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
7070
static const struct alpha_pll_config ipq5018_pll_config = {
7171
.l = 0x2a,
7272
.config_ctl_val = 0x4001075b,
73-
.config_ctl_hi_val = 0x304,
7473
.main_output_mask = BIT(0),
7574
.aux_output_mask = BIT(1),
7675
.early_output_mask = BIT(3),
@@ -84,7 +83,6 @@ static const struct alpha_pll_config ipq5018_pll_config = {
8483
static const struct alpha_pll_config ipq5332_pll_config = {
8584
.l = 0x2d,
8685
.config_ctl_val = 0x4001075b,
87-
.config_ctl_hi_val = 0x304,
8886
.main_output_mask = BIT(0),
8987
.aux_output_mask = BIT(1),
9088
.early_output_mask = BIT(3),

drivers/clk/qcom/clk-alpha-pll.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2574,6 +2574,9 @@ static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
25742574
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
25752575
a >> ALPHA_BITWIDTH);
25762576

2577+
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2578+
PLL_ALPHA_EN, PLL_ALPHA_EN);
2579+
25772580
regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
25782581

25792582
/* Wait five micro seconds or more */

drivers/clk/qcom/gcc-ipq9574.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2140,9 +2140,10 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
21402140

21412141
static struct clk_branch gcc_crypto_axi_clk = {
21422142
.halt_reg = 0x16010,
2143+
.halt_check = BRANCH_HALT_VOTED,
21432144
.clkr = {
2144-
.enable_reg = 0x16010,
2145-
.enable_mask = BIT(0),
2145+
.enable_reg = 0xb004,
2146+
.enable_mask = BIT(15),
21462147
.hw.init = &(const struct clk_init_data) {
21472148
.name = "gcc_crypto_axi_clk",
21482149
.parent_hws = (const struct clk_hw *[]) {
@@ -2156,9 +2157,10 @@ static struct clk_branch gcc_crypto_axi_clk = {
21562157

21572158
static struct clk_branch gcc_crypto_ahb_clk = {
21582159
.halt_reg = 0x16014,
2160+
.halt_check = BRANCH_HALT_VOTED,
21592161
.clkr = {
2160-
.enable_reg = 0x16014,
2161-
.enable_mask = BIT(0),
2162+
.enable_reg = 0xb004,
2163+
.enable_mask = BIT(16),
21622164
.hw.init = &(const struct clk_init_data) {
21632165
.name = "gcc_crypto_ahb_clk",
21642166
.parent_hws = (const struct clk_hw *[]) {

drivers/clk/qcom/gcc-sm6350.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,8 @@ static struct clk_alpha_pll gpll6 = {
100100
.enable_mask = BIT(6),
101101
.hw.init = &(struct clk_init_data){
102102
.name = "gpll6",
103-
.parent_hws = (const struct clk_hw*[]){
104-
&gpll0.clkr.hw,
103+
.parent_data = &(const struct clk_parent_data){
104+
.fw_name = "bi_tcxo",
105105
},
106106
.num_parents = 1,
107107
.ops = &clk_alpha_pll_fixed_fabia_ops,
@@ -124,7 +124,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_even = {
124124
.clkr.hw.init = &(struct clk_init_data){
125125
.name = "gpll6_out_even",
126126
.parent_hws = (const struct clk_hw*[]){
127-
&gpll0.clkr.hw,
127+
&gpll6.clkr.hw,
128128
},
129129
.num_parents = 1,
130130
.ops = &clk_alpha_pll_postdiv_fabia_ops,
@@ -139,8 +139,8 @@ static struct clk_alpha_pll gpll7 = {
139139
.enable_mask = BIT(7),
140140
.hw.init = &(struct clk_init_data){
141141
.name = "gpll7",
142-
.parent_hws = (const struct clk_hw*[]){
143-
&gpll0.clkr.hw,
142+
.parent_data = &(const struct clk_parent_data){
143+
.fw_name = "bi_tcxo",
144144
},
145145
.num_parents = 1,
146146
.ops = &clk_alpha_pll_fixed_fabia_ops,

0 commit comments

Comments
 (0)