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Nogah Frankeldavem330
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mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of which trap "wins" if a packet matches two traps (priority) and in terms of packets from which trap group will be scheduled to the cpu first (tc). They can also be used to set rate limiters (policers) on them (will be added in the next patches). Currently, we support two trap groups. In Spectrum we want a better resolution, so every protocol / flow will have a different trap group, so we can control its parameters separately. Once the policers will be implemented, it will also allow us limit the rate of each protocol by itself. This patch change the trap group list to include: * the emad trap group, which is shared for all the devices. * Switchx2's trap groups, which are a copy of the current trap groups. * Spectrum's new trap groups, in order to match the above guidelines. (Switchib is using only the emad trap group, so it require no changes). This patch also includes new configuration for Spectrum's trap groups, with primary priority order within them. Signed-off-by: Nogah Frankel <[email protected]> Signed-off-by: Jiri Pirko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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drivers/net/ethernet/mellanox/mlxsw/reg.h

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3034,8 +3034,21 @@ MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
30343034

30353035
enum mlxsw_reg_htgt_trap_group {
30363036
MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3037-
MLXSW_REG_HTGT_TRAP_GROUP_RX,
3038-
MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
3037+
MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
3038+
MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
3039+
MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
3040+
MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
3041+
MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
3042+
MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
3043+
MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4,
3044+
MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
3045+
MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
3046+
MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS,
3047+
MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
3048+
MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
3049+
MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
3050+
MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
3051+
MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
30393052
};
30403053

30413054
/* reg_htgt_trap_group

drivers/net/ethernet/mellanox/mlxsw/spectrum.c

Lines changed: 58 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2730,46 +2730,50 @@ static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
27302730
return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
27312731
}
27322732

2733-
#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _is_ctrl) \
2733+
#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
27342734
MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
2735-
_is_ctrl, RX, DISCARD)
2735+
_is_ctrl, SP_##_trap_group, DISCARD)
27362736

2737-
#define MLXSW_SP_RXL_MARK(_trap_id, _action, _is_ctrl) \
2737+
#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
27382738
MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
2739-
_is_ctrl, RX, DISCARD)
2739+
_is_ctrl, SP_##_trap_group, DISCARD)
2740+
2741+
#define MLXSW_SP_EVENTL(_func, _trap_id) \
2742+
MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
27402743

27412744
static const struct mlxsw_listener mlxsw_sp_listener[] = {
27422745
/* Events */
2743-
MLXSW_EVENTL(mlxsw_sp_pude_event_func, PUDE, EMAD),
2746+
MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
27442747
/* L2 traps */
2745-
MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, true),
2746-
MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, true),
2747-
MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, true),
2748-
MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, false),
2749-
MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, false),
2750-
MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, false),
2751-
MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, false),
2752-
MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, false),
2753-
MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, false),
2754-
MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, false),
2755-
MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, false),
2748+
MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
2749+
MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
2750+
MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
2751+
MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
2752+
MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
2753+
MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
2754+
MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
2755+
MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
2756+
MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
2757+
MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
2758+
MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
27562759
/* L3 traps */
2757-
MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, false),
2758-
MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, false),
2759-
MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, false),
2760-
MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, false),
2761-
MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, false),
2762-
MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, false),
2763-
MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, false),
2764-
MLXSW_SP_RXL_MARK(BGP_IPV4, TRAP_TO_CPU, false),
2760+
MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2761+
MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2762+
MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2763+
MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
2764+
MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
2765+
MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
2766+
MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
2767+
MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
27652768
};
27662769

27672770
static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
27682771
{
27692772
char htgt_pl[MLXSW_REG_HTGT_LEN];
2773+
enum mlxsw_reg_htgt_trap_group i;
27702774
int max_trap_groups;
27712775
u8 priority, tc;
2772-
int i, err;
2776+
int err;
27732777

27742778
if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
27752779
return -EIO;
@@ -2778,15 +2782,41 @@ static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
27782782

27792783
for (i = 0; i < max_trap_groups; i++) {
27802784
switch (i) {
2781-
case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
2782-
case MLXSW_REG_HTGT_TRAP_GROUP_RX:
2783-
case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
2785+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
2786+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
2787+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
2788+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
2789+
priority = 5;
2790+
tc = 5;
2791+
break;
2792+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
2793+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
2794+
priority = 4;
2795+
tc = 4;
2796+
break;
2797+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
2798+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
2799+
priority = 3;
2800+
tc = 3;
2801+
break;
2802+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
2803+
priority = 2;
2804+
tc = 2;
2805+
break;
2806+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
2807+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2808+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
2809+
priority = 1;
2810+
tc = 1;
2811+
break;
2812+
case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
27842813
priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
27852814
tc = MLXSW_REG_HTGT_DEFAULT_TC;
27862815
break;
27872816
default:
27882817
continue;
27892818
}
2819+
27902820
mlxsw_reg_htgt_pack(htgt_pl, i, MLXSW_REG_HTGT_INVALID_POLICER,
27912821
priority, tc);
27922822
err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);

drivers/net/ethernet/mellanox/mlxsw/switchx2.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1448,9 +1448,9 @@ static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
14481448
return err;
14491449
}
14501450

1451-
#define MLXSW_SX_RXL(_trap_id) \
1451+
#define MLXSW_SX_RXL(_trap_id) \
14521452
MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU, \
1453-
false, RX, FORWARD)
1453+
false, SX2_RX, FORWARD)
14541454

14551455
static const struct mlxsw_listener mlxsw_sx_listener[] = {
14561456
MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
@@ -1476,7 +1476,7 @@ static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
14761476
int i;
14771477
int err;
14781478

1479-
mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX,
1479+
mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
14801480
MLXSW_REG_HTGT_INVALID_POLICER,
14811481
MLXSW_REG_HTGT_DEFAULT_PRIORITY,
14821482
MLXSW_REG_HTGT_DEFAULT_TC);
@@ -1487,7 +1487,7 @@ static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
14871487
if (err)
14881488
return err;
14891489

1490-
mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
1490+
mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
14911491
MLXSW_REG_HTGT_INVALID_POLICER,
14921492
MLXSW_REG_HTGT_DEFAULT_PRIORITY,
14931493
MLXSW_REG_HTGT_DEFAULT_TC);

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