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torvaldstorvalds
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (41 commits) sctp: user perfect name for Delayed SACK Timer option net: fix can_checksum_protocol() arguments swap Revert "netlink: test for all flags of the NLM_F_DUMP composite" gianfar: Fix misleading indentation in startup_gfar() net/irda/sh_irda: return to RX mode when TX error net offloading: Do not mask out NETIF_F_HW_VLAN_TX for vlan. USB CDC NCM: tx_fixup() race condition fix ns83820: Avoid bad pointer deref in ns83820_init_one(). ipv6: Silence privacy extensions initialization bnx2x: Update bnx2x version to 1.62.00-4 bnx2x: Fix AER setting for BCM57712 bnx2x: Fix BCM84823 LED behavior bnx2x: Mark full duplex on some external PHYs bnx2x: Fix BCM8073/BCM8727 microcode loading bnx2x: LED fix for BCM8727 over BCM57712 bnx2x: Common init will be executed only once after POR bnx2x: Swap BCM8073 PHY polarity if required iwlwifi: fix valid chain reading from EEPROM ath5k: fix locking in tx_complete_poll_work ath9k_hw: do PA offset calibration only on longcal interval ...
2 parents c56eb8f + 4580ccc commit 1268afe

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41 files changed

+512
-258
lines changed

‎drivers/net/bnx2x/bnx2x.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,8 @@
2222
* (you will need to reboot afterwards) */
2323
/* #define BNX2X_STOP_ON_ERROR */
2424

25-
#define DRV_MODULE_VERSION "1.62.00-3"
26-
#define DRV_MODULE_RELDATE "2010/12/21"
25+
#define DRV_MODULE_VERSION "1.62.00-4"
26+
#define DRV_MODULE_RELDATE "2011/01/18"
2727
#define BNX2X_BC_VER 0x040200
2828

2929
#define BNX2X_MULTI_QUEUE

‎drivers/net/bnx2x/bnx2x_hsi.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -352,6 +352,10 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
352352
#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
353353
/* forced only */
354354
#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
355+
/* Indicate whether to swap the external phy polarity */
356+
#define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
357+
#define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
358+
#define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
355359

356360
u32 external_phy_config;
357361
#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000

‎drivers/net/bnx2x/bnx2x_link.c

Lines changed: 139 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1573,7 +1573,7 @@ static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
15731573

15741574
offset = phy->addr + ser_lane;
15751575
if (CHIP_IS_E2(bp))
1576-
aer_val = 0x2800 + offset - 1;
1576+
aer_val = 0x3800 + offset - 1;
15771577
else
15781578
aer_val = 0x3800 + offset;
15791579
CL45_WR_OVER_CL22(bp, phy,
@@ -3166,7 +3166,23 @@ u8 bnx2x_set_led(struct link_params *params,
31663166
if (!vars->link_up)
31673167
break;
31683168
case LED_MODE_ON:
3169-
if (SINGLE_MEDIA_DIRECT(params)) {
3169+
if (params->phy[EXT_PHY1].type ==
3170+
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 &&
3171+
CHIP_IS_E2(bp) && params->num_phys == 2) {
3172+
/**
3173+
* This is a work-around for E2+8727 Configurations
3174+
*/
3175+
if (mode == LED_MODE_ON ||
3176+
speed == SPEED_10000){
3177+
REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3178+
REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3179+
3180+
tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3181+
EMAC_WR(bp, EMAC_REG_EMAC_LED,
3182+
(tmp | EMAC_LED_OVERRIDE));
3183+
return rc;
3184+
}
3185+
} else if (SINGLE_MEDIA_DIRECT(params)) {
31703186
/**
31713187
* This is a work-around for HW issue found when link
31723188
* is up in CL73
@@ -3854,11 +3870,14 @@ static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
38543870
pause_result);
38553871
}
38563872
}
3857-
3858-
static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3873+
static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
38593874
struct bnx2x_phy *phy,
38603875
u8 port)
38613876
{
3877+
u32 count = 0;
3878+
u16 fw_ver1, fw_msgout;
3879+
u8 rc = 0;
3880+
38623881
/* Boot port from external ROM */
38633882
/* EDC grst */
38643883
bnx2x_cl45_write(bp, phy,
@@ -3888,14 +3907,45 @@ static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
38883907
MDIO_PMA_REG_GEN_CTRL,
38893908
MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
38903909

3891-
/* wait for 120ms for code download via SPI port */
3892-
msleep(120);
3910+
/* Delay 100ms per the PHY specifications */
3911+
msleep(100);
3912+
3913+
/* 8073 sometimes taking longer to download */
3914+
do {
3915+
count++;
3916+
if (count > 300) {
3917+
DP(NETIF_MSG_LINK,
3918+
"bnx2x_8073_8727_external_rom_boot port %x:"
3919+
"Download failed. fw version = 0x%x\n",
3920+
port, fw_ver1);
3921+
rc = -EINVAL;
3922+
break;
3923+
}
3924+
3925+
bnx2x_cl45_read(bp, phy,
3926+
MDIO_PMA_DEVAD,
3927+
MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3928+
bnx2x_cl45_read(bp, phy,
3929+
MDIO_PMA_DEVAD,
3930+
MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3931+
3932+
msleep(1);
3933+
} while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3934+
((fw_msgout & 0xff) != 0x03 && (phy->type ==
3935+
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
38933936

38943937
/* Clear ser_boot_ctl bit */
38953938
bnx2x_cl45_write(bp, phy,
38963939
MDIO_PMA_DEVAD,
38973940
MDIO_PMA_REG_MISC_CTRL1, 0x0000);
38983941
bnx2x_save_bcm_spirom_ver(bp, phy, port);
3942+
3943+
DP(NETIF_MSG_LINK,
3944+
"bnx2x_8073_8727_external_rom_boot port %x:"
3945+
"Download complete. fw version = 0x%x\n",
3946+
port, fw_ver1);
3947+
3948+
return rc;
38993949
}
39003950

39013951
static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
@@ -4108,6 +4158,25 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
41084158

41094159
DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
41104160

4161+
/**
4162+
* If this is forced speed, set to KR or KX (all other are not
4163+
* supported)
4164+
*/
4165+
/* Swap polarity if required - Must be done only in non-1G mode */
4166+
if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4167+
/* Configure the 8073 to swap _P and _N of the KR lines */
4168+
DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4169+
/* 10G Rx/Tx and 1G Tx signal polarity swap */
4170+
bnx2x_cl45_read(bp, phy,
4171+
MDIO_PMA_DEVAD,
4172+
MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4173+
bnx2x_cl45_write(bp, phy,
4174+
MDIO_PMA_DEVAD,
4175+
MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4176+
(val | (3<<9)));
4177+
}
4178+
4179+
41114180
/* Enable CL37 BAM */
41124181
if (REG_RD(bp, params->shmem_base +
41134182
offsetof(struct shmem_region, dev_info.
@@ -4314,8 +4383,32 @@ static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
43144383
}
43154384

43164385
if (link_up) {
4386+
/* Swap polarity if required */
4387+
if (params->lane_config &
4388+
PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4389+
/* Configure the 8073 to swap P and N of the KR lines */
4390+
bnx2x_cl45_read(bp, phy,
4391+
MDIO_XS_DEVAD,
4392+
MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4393+
/**
4394+
* Set bit 3 to invert Rx in 1G mode and clear this bit
4395+
* when it`s in 10G mode.
4396+
*/
4397+
if (vars->line_speed == SPEED_1000) {
4398+
DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4399+
"the 8073\n");
4400+
val1 |= (1<<3);
4401+
} else
4402+
val1 &= ~(1<<3);
4403+
4404+
bnx2x_cl45_write(bp, phy,
4405+
MDIO_XS_DEVAD,
4406+
MDIO_XS_REG_8073_RX_CTRL_PCIE,
4407+
val1);
4408+
}
43174409
bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
43184410
bnx2x_8073_resolve_fc(phy, params, vars);
4411+
vars->duplex = DUPLEX_FULL;
43194412
}
43204413
return link_up;
43214414
}
@@ -5062,6 +5155,7 @@ static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
50625155
else
50635156
vars->line_speed = SPEED_10000;
50645157
bnx2x_ext_phy_resolve_fc(phy, params, vars);
5158+
vars->duplex = DUPLEX_FULL;
50655159
}
50665160
return link_up;
50675161
}
@@ -5758,8 +5852,11 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
57585852
DP(NETIF_MSG_LINK, "port %x: External link is down\n",
57595853
params->port);
57605854
}
5761-
if (link_up)
5855+
if (link_up) {
57625856
bnx2x_ext_phy_resolve_fc(phy, params, vars);
5857+
vars->duplex = DUPLEX_FULL;
5858+
DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
5859+
}
57635860

57645861
if ((DUAL_MEDIA(params)) &&
57655862
(phy->req_line_speed == SPEED_1000)) {
@@ -5875,10 +5972,26 @@ static void bnx2x_848xx_set_led(struct bnx2x *bp,
58755972
MDIO_PMA_REG_8481_LED2_MASK,
58765973
0x18);
58775974

5975+
/* Select activity source by Tx and Rx, as suggested by PHY AE */
58785976
bnx2x_cl45_write(bp, phy,
58795977
MDIO_PMA_DEVAD,
58805978
MDIO_PMA_REG_8481_LED3_MASK,
5881-
0x0040);
5979+
0x0006);
5980+
5981+
/* Select the closest activity blink rate to that in 10/100/1000 */
5982+
bnx2x_cl45_write(bp, phy,
5983+
MDIO_PMA_DEVAD,
5984+
MDIO_PMA_REG_8481_LED3_BLINK,
5985+
0);
5986+
5987+
bnx2x_cl45_read(bp, phy,
5988+
MDIO_PMA_DEVAD,
5989+
MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
5990+
val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
5991+
5992+
bnx2x_cl45_write(bp, phy,
5993+
MDIO_PMA_DEVAD,
5994+
MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
58825995

58835996
/* 'Interrupt Mask' */
58845997
bnx2x_cl45_write(bp, phy,
@@ -6126,6 +6239,7 @@ static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
61266239
/* Check link 10G */
61276240
if (val2 & (1<<11)) {
61286241
vars->line_speed = SPEED_10000;
6242+
vars->duplex = DUPLEX_FULL;
61296243
link_up = 1;
61306244
bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
61316245
} else { /* Check Legacy speed link */
@@ -6489,6 +6603,7 @@ static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
64896603
MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
64906604
&val2);
64916605
vars->line_speed = SPEED_10000;
6606+
vars->duplex = DUPLEX_FULL;
64926607
DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
64936608
val2, (val2 & (1<<14)));
64946609
bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
@@ -7663,27 +7778,16 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
76637778

76647779
/* PART2 - Download firmware to both phys */
76657780
for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7666-
u16 fw_ver1;
76677781
if (CHIP_IS_E2(bp))
76687782
port_of_path = 0;
76697783
else
76707784
port_of_path = port;
76717785

76727786
DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
76737787
phy_blk[port]->addr);
7674-
bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7675-
port_of_path);
7676-
7677-
bnx2x_cl45_read(bp, phy_blk[port],
7678-
MDIO_PMA_DEVAD,
7679-
MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7680-
if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7681-
DP(NETIF_MSG_LINK,
7682-
"bnx2x_8073_common_init_phy port %x:"
7683-
"Download failed. fw version = 0x%x\n",
7684-
port, fw_ver1);
7788+
if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7789+
port_of_path))
76857790
return -EINVAL;
7686-
}
76877791

76887792
/* Only set bit 10 = 1 (Tx power down) */
76897793
bnx2x_cl45_read(bp, phy_blk[port],
@@ -7848,27 +7952,17 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
78487952
}
78497953
/* PART2 - Download firmware to both phys */
78507954
for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7851-
u16 fw_ver1;
78527955
if (CHIP_IS_E2(bp))
78537956
port_of_path = 0;
78547957
else
78557958
port_of_path = port;
78567959
DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
78577960
phy_blk[port]->addr);
7858-
bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7859-
port_of_path);
7860-
bnx2x_cl45_read(bp, phy_blk[port],
7861-
MDIO_PMA_DEVAD,
7862-
MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7863-
if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7864-
DP(NETIF_MSG_LINK,
7865-
"bnx2x_8727_common_init_phy port %x:"
7866-
"Download failed. fw version = 0x%x\n",
7867-
port, fw_ver1);
7961+
if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7962+
port_of_path))
78687963
return -EINVAL;
7869-
}
7870-
}
78717964

7965+
}
78727966
return 0;
78737967
}
78747968

@@ -7916,13 +8010,24 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
79168010
u32 shmem2_base_path[], u32 chip_id)
79178011
{
79188012
u8 rc = 0;
8013+
u32 phy_ver;
79198014
u8 phy_index;
79208015
u32 ext_phy_type, ext_phy_config;
79218016
DP(NETIF_MSG_LINK, "Begin common phy init\n");
79228017

79238018
if (CHIP_REV_IS_EMUL(bp))
79248019
return 0;
79258020

8021+
/* Check if common init was already done */
8022+
phy_ver = REG_RD(bp, shmem_base_path[0] +
8023+
offsetof(struct shmem_region,
8024+
port_mb[PORT_0].ext_phy_fw_version));
8025+
if (phy_ver) {
8026+
DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8027+
phy_ver);
8028+
return 0;
8029+
}
8030+
79268031
/* Read the ext_phy_type for arbitrary port(0) */
79278032
for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
79288033
phy_index++) {

‎drivers/net/bnx2x/bnx2x_reg.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6194,7 +6194,11 @@ Theotherbitsarereservedandshouldbezero*/
61946194
#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
61956195
#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
61966196
#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
6197+
#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
6198+
#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
61976199

6200+
#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
6201+
#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
61986202

61996203
#define IGU_FUNC_BASE 0x0400
62006204

‎drivers/net/gianfar.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1920,7 +1920,7 @@ int startup_gfar(struct net_device *ndev)
19201920
if (err) {
19211921
for (j = 0; j < i; j++)
19221922
free_grp_irqs(&priv->gfargrp[j]);
1923-
goto irq_fail;
1923+
goto irq_fail;
19241924
}
19251925
}
19261926

‎drivers/net/irda/sh_irda.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -635,7 +635,7 @@ static int sh_irda_hard_xmit(struct sk_buff *skb, struct net_device *ndev)
635635

636636
ret = sh_irda_set_baudrate(self, speed);
637637
if (ret < 0)
638-
return ret;
638+
goto sh_irda_hard_xmit_end;
639639

640640
self->tx_buff.len = 0;
641641
if (skb->len) {
@@ -652,11 +652,21 @@ static int sh_irda_hard_xmit(struct sk_buff *skb, struct net_device *ndev)
652652

653653
sh_irda_write(self, IRTFLR, self->tx_buff.len);
654654
sh_irda_write(self, IRTCTR, ARMOD | TE);
655-
}
655+
} else
656+
goto sh_irda_hard_xmit_end;
656657

657658
dev_kfree_skb(skb);
658659

659660
return 0;
661+
662+
sh_irda_hard_xmit_end:
663+
sh_irda_set_baudrate(self, 9600);
664+
netif_wake_queue(self->ndev);
665+
sh_irda_rcv_ctrl(self, 1);
666+
dev_kfree_skb(skb);
667+
668+
return ret;
669+
660670
}
661671

662672
static int sh_irda_ioctl(struct net_device *ndev, struct ifreq *ifreq, int cmd)

‎drivers/net/ns83820.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1988,12 +1988,11 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev,
19881988
}
19891989

19901990
ndev = alloc_etherdev(sizeof(struct ns83820));
1991-
dev = PRIV(ndev);
1992-
19931991
err = -ENOMEM;
1994-
if (!dev)
1992+
if (!ndev)
19951993
goto out;
19961994

1995+
dev = PRIV(ndev);
19971996
dev->ndev = ndev;
19981997

19991998
spin_lock_init(&dev->rx_info.lock);

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