Skip to content

Commit 148f472

Browse files
idoschdavem330
authored andcommitted
mlxsw: reg: Add the Switch Port Acceptable Frame Types register
When VLAN filtering is enabled on a bridge and PVID is deleted from a bridge port, then untagged frames are not allowed to ingress into the bridge from this port. Add the Switch Port Acceptable Frame Types (SPAFT) register, which configures the frame admittance of the port. Fixes: 56ade8f ("mlxsw: spectrum: Add initial support for Spectrum ASIC") Signed-off-by: Ido Schimmel <[email protected]> Signed-off-by: Jiri Pirko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
1 parent 562a9f9 commit 148f472

File tree

1 file changed

+58
-0
lines changed
  • drivers/net/ethernet/mellanox/mlxsw

1 file changed

+58
-0
lines changed

drivers/net/ethernet/mellanox/mlxsw/reg.h

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -873,6 +873,62 @@ static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
873873
}
874874
}
875875

876+
/* SPAFT - Switch Port Acceptable Frame Types
877+
* ------------------------------------------
878+
* The Switch Port Acceptable Frame Types register configures the frame
879+
* admittance of the port.
880+
*/
881+
#define MLXSW_REG_SPAFT_ID 0x2010
882+
#define MLXSW_REG_SPAFT_LEN 0x08
883+
884+
static const struct mlxsw_reg_info mlxsw_reg_spaft = {
885+
.id = MLXSW_REG_SPAFT_ID,
886+
.len = MLXSW_REG_SPAFT_LEN,
887+
};
888+
889+
/* reg_spaft_local_port
890+
* Local port number.
891+
* Access: Index
892+
*
893+
* Note: CPU port is not supported (all tag types are allowed).
894+
*/
895+
MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
896+
897+
/* reg_spaft_sub_port
898+
* Virtual port within the physical port.
899+
* Should be set to 0 when virtual ports are not enabled on the port.
900+
* Access: RW
901+
*/
902+
MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
903+
904+
/* reg_spaft_allow_untagged
905+
* When set, untagged frames on the ingress are allowed (default).
906+
* Access: RW
907+
*/
908+
MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
909+
910+
/* reg_spaft_allow_prio_tagged
911+
* When set, priority tagged frames on the ingress are allowed (default).
912+
* Access: RW
913+
*/
914+
MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
915+
916+
/* reg_spaft_allow_tagged
917+
* When set, tagged frames on the ingress are allowed (default).
918+
* Access: RW
919+
*/
920+
MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
921+
922+
static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
923+
bool allow_untagged)
924+
{
925+
MLXSW_REG_ZERO(spaft, payload);
926+
mlxsw_reg_spaft_local_port_set(payload, local_port);
927+
mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
928+
mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
929+
mlxsw_reg_spaft_allow_tagged_set(payload, true);
930+
}
931+
876932
/* SFGC - Switch Flooding Group Configuration
877933
* ------------------------------------------
878934
* The following register controls the association of flooding tables and MIDs
@@ -3203,6 +3259,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
32033259
return "SPVID";
32043260
case MLXSW_REG_SPVM_ID:
32053261
return "SPVM";
3262+
case MLXSW_REG_SPAFT_ID:
3263+
return "SPAFT";
32063264
case MLXSW_REG_SFGC_ID:
32073265
return "SFGC";
32083266
case MLXSW_REG_SFTR_ID:

0 commit comments

Comments
 (0)