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35 | 35 | #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \
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36 | 36 | iface == PHY_INTERFACE_MODE_GMII)
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37 | 37 |
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38 |
| -/* STiH4xx register definitions (STiH415/STiH416/STiH407/STiH410 families) |
| 38 | +/* STiH4xx register definitions (STiH407/STiH410 families) |
39 | 39 | *
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40 | 40 | * Below table summarizes the clock requirement and clock sources for
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41 | 41 | * supported phy interface modes with link speeds.
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75 | 75 | #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
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76 | 76 | #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
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77 | 77 |
|
78 |
| -/* STiD127 register definitions |
79 |
| - *----------------------- |
80 |
| - * src |BIT(6)| BIT(7)| |
81 |
| - *----------------------- |
82 |
| - * MII | 1 | n/a | |
83 |
| - *----------------------- |
84 |
| - * RMII | n/a | 1 | |
85 |
| - * clkgen| | | |
86 |
| - *----------------------- |
87 |
| - * RMII | n/a | 0 | |
88 |
| - * phyclk| | | |
89 |
| - *----------------------- |
90 |
| - * RGMII | 1 | n/a | |
91 |
| - * clkgen| | | |
92 |
| - *----------------------- |
93 |
| - */ |
94 |
| - |
95 |
| -#define STID127_RETIME_SRC_MASK GENMASK(7, 6) |
96 |
| -#define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) |
97 |
| -#define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6) |
98 |
| - |
99 | 78 | #define ENMII_MASK GENMASK(5, 5)
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100 | 79 | #define ENMII BIT(5)
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101 | 80 | #define EN_MASK GENMASK(1, 1)
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@@ -194,36 +173,6 @@ static void stih4xx_fix_retime_src(void *priv, u32 spd)
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194 | 173 | stih4xx_tx_retime_val[src]);
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195 | 174 | }
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196 | 175 |
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197 |
| -static void stid127_fix_retime_src(void *priv, u32 spd) |
198 |
| -{ |
199 |
| - struct sti_dwmac *dwmac = priv; |
200 |
| - u32 reg = dwmac->ctrl_reg; |
201 |
| - u32 freq = 0; |
202 |
| - u32 val = 0; |
203 |
| - |
204 |
| - if (dwmac->interface == PHY_INTERFACE_MODE_MII) { |
205 |
| - val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; |
206 |
| - } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { |
207 |
| - if (!dwmac->ext_phyclk) { |
208 |
| - val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK; |
209 |
| - freq = DWMAC_50MHZ; |
210 |
| - } |
211 |
| - } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { |
212 |
| - val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; |
213 |
| - if (spd == SPEED_1000) |
214 |
| - freq = DWMAC_125MHZ; |
215 |
| - else if (spd == SPEED_100) |
216 |
| - freq = DWMAC_25MHZ; |
217 |
| - else if (spd == SPEED_10) |
218 |
| - freq = DWMAC_2_5MHZ; |
219 |
| - } |
220 |
| - |
221 |
| - if (freq) |
222 |
| - clk_set_rate(dwmac->clk, freq); |
223 |
| - |
224 |
| - regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); |
225 |
| -} |
226 |
| - |
227 | 176 | static int sti_dwmac_set_mode(struct sti_dwmac *dwmac)
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228 | 177 | {
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229 | 178 | struct regmap *regmap = dwmac->regmap;
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@@ -408,14 +357,7 @@ static const struct sti_dwmac_of_data stih4xx_dwmac_data = {
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408 | 357 | .fix_retime_src = stih4xx_fix_retime_src,
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409 | 358 | };
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410 | 359 |
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411 |
| -static const struct sti_dwmac_of_data stid127_dwmac_data = { |
412 |
| - .fix_retime_src = stid127_fix_retime_src, |
413 |
| -}; |
414 |
| - |
415 | 360 | static const struct of_device_id sti_dwmac_match[] = {
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416 |
| - { .compatible = "st,stih415-dwmac", .data = &stih4xx_dwmac_data}, |
417 |
| - { .compatible = "st,stih416-dwmac", .data = &stih4xx_dwmac_data}, |
418 |
| - { .compatible = "st,stid127-dwmac", .data = &stid127_dwmac_data}, |
419 | 361 | { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data},
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420 | 362 | { }
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421 | 363 | };
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