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Merge tag 'drm-fixes-for-v4.16-rc6' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "i915, amd and nouveau fixes. i915: - backlight fix for some panels - pm fix - fencing fix - some GVT fixes amdgpu: - backlight fix across suspend/resume - object destruction ordering issue fix - displayport fix nouveau: - two backlight fixes - fix for some lockups Pretty quiet week, seems like everyone was fixing backlights" * tag 'drm-fixes-for-v4.16-rc6' of git://people.freedesktop.org/~airlied/linux: drm/nouveau/bl: fix backlight regression drm/nouveau/bl: Fix oops on driver unbind drm/nouveau/mmu: ALIGN_DOWN correct variable drm/i915/gvt: fix user copy warning by whitelist workload rb_tail field drm/i915/gvt: Correct the privilege shadow batch buffer address drm/amdgpu/dce: Don't turn off DP sink when disconnected drm/amdgpu: save/restore backlight level in legacy dce code drm/radeon: fix prime teardown order drm/amdgpu: fix prime teardown order drm/i915: Kick the rps worker when changing the boost frequency drm/i915: Only prune fences after wait-for-all drm/i915: Enable VBT based BL control for DP drm/i915/gvt: keep oa config in shadow ctx drm/i915/gvt: Add runtime_pm_get/put into gvt_switch_mmio
2 parents df09348 + 3a1b5de commit 1660a76

21 files changed

+169
-50
lines changed

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

Lines changed: 12 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -69,25 +69,18 @@ void amdgpu_connector_hotplug(struct drm_connector *connector)
6969
/* don't do anything if sink is not display port, i.e.,
7070
* passive dp->(dvi|hdmi) adaptor
7171
*/
72-
if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
73-
int saved_dpms = connector->dpms;
74-
/* Only turn off the display if it's physically disconnected */
75-
if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
76-
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
77-
} else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
78-
/* Don't try to start link training before we
79-
* have the dpcd */
80-
if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
81-
return;
82-
83-
/* set it to OFF so that drm_helper_connector_dpms()
84-
* won't return immediately since the current state
85-
* is ON at this point.
86-
*/
87-
connector->dpms = DRM_MODE_DPMS_OFF;
88-
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
89-
}
90-
connector->dpms = saved_dpms;
72+
if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
73+
amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
74+
amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
75+
/* Don't start link training before we have the DPCD */
76+
if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
77+
return;
78+
79+
/* Turn the connector off and back on immediately, which
80+
* will trigger link training
81+
*/
82+
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
83+
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
9184
}
9285
}
9386
}

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,6 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj)
3636
struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
3737

3838
if (robj) {
39-
if (robj->gem_base.import_attach)
40-
drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
4139
amdgpu_mn_unregister(robj);
4240
amdgpu_bo_unref(&robj);
4341
}

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -352,6 +352,7 @@ struct amdgpu_mode_info {
352352
u16 firmware_flags;
353353
/* pointer to backlight encoder */
354354
struct amdgpu_encoder *bl_encoder;
355+
u8 bl_level; /* saved backlight level */
355356
struct amdgpu_audio audio; /* audio stuff */
356357
int num_crtc; /* number of crtcs */
357358
int num_hpd; /* number of hpd pins */

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,8 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
5656

5757
amdgpu_bo_kunmap(bo);
5858

59+
if (bo->gem_base.import_attach)
60+
drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
5961
drm_gem_object_release(&bo->gem_base);
6062
amdgpu_bo_unref(&bo->parent);
6163
if (!list_empty(&bo->shadow_list)) {

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@
3434
#include <linux/backlight.h>
3535
#include "bif/bif_4_1_d.h"
3636

37-
static u8
37+
u8
3838
amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
3939
{
4040
u8 backlight_level;
@@ -48,7 +48,7 @@ amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
4848
return backlight_level;
4949
}
5050

51-
static void
51+
void
5252
amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
5353
u8 backlight_level)
5454
{

drivers/gpu/drm/amd/amdgpu/atombios_encoders.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,11 @@
2424
#ifndef __ATOMBIOS_ENCODER_H__
2525
#define __ATOMBIOS_ENCODER_H__
2626

27+
u8
28+
amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev);
29+
void
30+
amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
31+
u8 backlight_level);
2732
u8
2833
amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder);
2934
void

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2921,6 +2921,11 @@ static int dce_v10_0_hw_fini(void *handle)
29212921

29222922
static int dce_v10_0_suspend(void *handle)
29232923
{
2924+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2925+
2926+
adev->mode_info.bl_level =
2927+
amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2928+
29242929
return dce_v10_0_hw_fini(handle);
29252930
}
29262931

@@ -2929,6 +2934,9 @@ static int dce_v10_0_resume(void *handle)
29292934
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
29302935
int ret;
29312936

2937+
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2938+
adev->mode_info.bl_level);
2939+
29322940
ret = dce_v10_0_hw_init(handle);
29332941

29342942
/* turn on the BL */

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3047,6 +3047,11 @@ static int dce_v11_0_hw_fini(void *handle)
30473047

30483048
static int dce_v11_0_suspend(void *handle)
30493049
{
3050+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3051+
3052+
adev->mode_info.bl_level =
3053+
amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3054+
30503055
return dce_v11_0_hw_fini(handle);
30513056
}
30523057

@@ -3055,6 +3060,9 @@ static int dce_v11_0_resume(void *handle)
30553060
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
30563061
int ret;
30573062

3063+
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3064+
adev->mode_info.bl_level);
3065+
30583066
ret = dce_v11_0_hw_init(handle);
30593067

30603068
/* turn on the BL */

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2787,6 +2787,11 @@ static int dce_v6_0_hw_fini(void *handle)
27872787

27882788
static int dce_v6_0_suspend(void *handle)
27892789
{
2790+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2791+
2792+
adev->mode_info.bl_level =
2793+
amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2794+
27902795
return dce_v6_0_hw_fini(handle);
27912796
}
27922797

@@ -2795,6 +2800,9 @@ static int dce_v6_0_resume(void *handle)
27952800
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
27962801
int ret;
27972802

2803+
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2804+
adev->mode_info.bl_level);
2805+
27982806
ret = dce_v6_0_hw_init(handle);
27992807

28002808
/* turn on the BL */

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2819,6 +2819,11 @@ static int dce_v8_0_hw_fini(void *handle)
28192819

28202820
static int dce_v8_0_suspend(void *handle)
28212821
{
2822+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2823+
2824+
adev->mode_info.bl_level =
2825+
amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2826+
28222827
return dce_v8_0_hw_fini(handle);
28232828
}
28242829

@@ -2827,6 +2832,9 @@ static int dce_v8_0_resume(void *handle)
28272832
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
28282833
int ret;
28292834

2835+
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2836+
adev->mode_info.bl_level);
2837+
28302838
ret = dce_v8_0_hw_init(handle);
28312839

28322840
/* turn on the BL */

drivers/gpu/drm/i915/gvt/cmd_parser.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -471,6 +471,7 @@ struct parser_exec_state {
471471
* used when ret from 2nd level batch buffer
472472
*/
473473
int saved_buf_addr_type;
474+
bool is_ctx_wa;
474475

475476
struct cmd_info *info;
476477

@@ -1715,6 +1716,11 @@ static int perform_bb_shadow(struct parser_exec_state *s)
17151716
bb->accessing = true;
17161717
bb->bb_start_cmd_va = s->ip_va;
17171718

1719+
if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1720+
bb->bb_offset = s->ip_va - s->rb_va;
1721+
else
1722+
bb->bb_offset = 0;
1723+
17181724
/*
17191725
* ip_va saves the virtual address of the shadow batch buffer, while
17201726
* ip_gma saves the graphics address of the original batch buffer.
@@ -2571,6 +2577,7 @@ static int scan_workload(struct intel_vgpu_workload *workload)
25712577
s.ring_tail = gma_tail;
25722578
s.rb_va = workload->shadow_ring_buffer_va;
25732579
s.workload = workload;
2580+
s.is_ctx_wa = false;
25742581

25752582
if ((bypass_scan_mask & (1 << workload->ring_id)) ||
25762583
gma_head == gma_tail)
@@ -2624,6 +2631,7 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
26242631
s.ring_tail = gma_tail;
26252632
s.rb_va = wa_ctx->indirect_ctx.shadow_va;
26262633
s.workload = workload;
2634+
s.is_ctx_wa = true;
26272635

26282636
if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
26292637
ret = -EINVAL;

drivers/gpu/drm/i915/gvt/mmio_context.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -394,9 +394,11 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
394394
* performace for batch mmio read/write, so we need
395395
* handle forcewake mannually.
396396
*/
397+
intel_runtime_pm_get(dev_priv);
397398
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
398399
switch_mmio(pre, next, ring_id);
399400
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
401+
intel_runtime_pm_put(dev_priv);
400402
}
401403

402404
/**

drivers/gpu/drm/i915/gvt/scheduler.c

Lines changed: 67 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,54 @@ static void set_context_pdp_root_pointer(
5252
pdp_pair[i].val = pdp[7 - i];
5353
}
5454

55+
/*
56+
* when populating shadow ctx from guest, we should not overrride oa related
57+
* registers, so that they will not be overlapped by guest oa configs. Thus
58+
* made it possible to capture oa data from host for both host and guests.
59+
*/
60+
static void sr_oa_regs(struct intel_vgpu_workload *workload,
61+
u32 *reg_state, bool save)
62+
{
63+
struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
64+
u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
65+
u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
66+
int i = 0;
67+
u32 flex_mmio[] = {
68+
i915_mmio_reg_offset(EU_PERF_CNTL0),
69+
i915_mmio_reg_offset(EU_PERF_CNTL1),
70+
i915_mmio_reg_offset(EU_PERF_CNTL2),
71+
i915_mmio_reg_offset(EU_PERF_CNTL3),
72+
i915_mmio_reg_offset(EU_PERF_CNTL4),
73+
i915_mmio_reg_offset(EU_PERF_CNTL5),
74+
i915_mmio_reg_offset(EU_PERF_CNTL6),
75+
};
76+
77+
if (!workload || !reg_state || workload->ring_id != RCS)
78+
return;
79+
80+
if (save) {
81+
workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
82+
83+
for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
84+
u32 state_offset = ctx_flexeu0 + i * 2;
85+
86+
workload->flex_mmio[i] = reg_state[state_offset + 1];
87+
}
88+
} else {
89+
reg_state[ctx_oactxctrl] =
90+
i915_mmio_reg_offset(GEN8_OACTXCONTROL);
91+
reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
92+
93+
for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
94+
u32 state_offset = ctx_flexeu0 + i * 2;
95+
u32 mmio = flex_mmio[i];
96+
97+
reg_state[state_offset] = mmio;
98+
reg_state[state_offset + 1] = workload->flex_mmio[i];
99+
}
100+
}
101+
}
102+
55103
static int populate_shadow_context(struct intel_vgpu_workload *workload)
56104
{
57105
struct intel_vgpu *vgpu = workload->vgpu;
@@ -98,6 +146,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
98146
page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
99147
shadow_ring_context = kmap(page);
100148

149+
sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
101150
#define COPY_REG(name) \
102151
intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
103152
+ RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
@@ -122,6 +171,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
122171
sizeof(*shadow_ring_context),
123172
I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
124173

174+
sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
125175
kunmap(page);
126176
return 0;
127177
}
@@ -376,6 +426,17 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
376426
goto err;
377427
}
378428

429+
/* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
430+
* is only updated into ring_scan_buffer, not real ring address
431+
* allocated in later copy_workload_to_ring_buffer. pls be noted
432+
* shadow_ring_buffer_va is now pointed to real ring buffer va
433+
* in copy_workload_to_ring_buffer.
434+
*/
435+
436+
if (bb->bb_offset)
437+
bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
438+
+ bb->bb_offset;
439+
379440
/* relocate shadow batch buffer */
380441
bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
381442
if (gmadr_bytes == 8)
@@ -1044,10 +1105,12 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
10441105

10451106
bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
10461107

1047-
s->workloads = kmem_cache_create("gvt-g_vgpu_workload",
1048-
sizeof(struct intel_vgpu_workload), 0,
1049-
SLAB_HWCACHE_ALIGN,
1050-
NULL);
1108+
s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1109+
sizeof(struct intel_vgpu_workload), 0,
1110+
SLAB_HWCACHE_ALIGN,
1111+
offsetof(struct intel_vgpu_workload, rb_tail),
1112+
sizeof_field(struct intel_vgpu_workload, rb_tail),
1113+
NULL);
10511114

10521115
if (!s->workloads) {
10531116
ret = -ENOMEM;

drivers/gpu/drm/i915/gvt/scheduler.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,10 @@ struct intel_vgpu_workload {
110110
/* shadow batch buffer */
111111
struct list_head shadow_bb;
112112
struct intel_shadow_wa_ctx wa_ctx;
113+
114+
/* oa registers */
115+
u32 oactxctrl;
116+
u32 flex_mmio[7];
113117
};
114118

115119
struct intel_vgpu_shadow_bb {
@@ -120,6 +124,7 @@ struct intel_vgpu_shadow_bb {
120124
u32 *bb_start_cmd_va;
121125
unsigned int clflush;
122126
bool accessing;
127+
unsigned long bb_offset;
123128
};
124129

125130
#define workload_q_head(vgpu, ring_id) \

drivers/gpu/drm/i915/i915_gem.c

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -434,20 +434,28 @@ i915_gem_object_wait_reservation(struct reservation_object *resv,
434434
dma_fence_put(shared[i]);
435435
kfree(shared);
436436

437+
/*
438+
* If both shared fences and an exclusive fence exist,
439+
* then by construction the shared fences must be later
440+
* than the exclusive fence. If we successfully wait for
441+
* all the shared fences, we know that the exclusive fence
442+
* must all be signaled. If all the shared fences are
443+
* signaled, we can prune the array and recover the
444+
* floating references on the fences/requests.
445+
*/
437446
prune_fences = count && timeout >= 0;
438447
} else {
439448
excl = reservation_object_get_excl_rcu(resv);
440449
}
441450

442-
if (excl && timeout >= 0) {
451+
if (excl && timeout >= 0)
443452
timeout = i915_gem_object_wait_fence(excl, flags, timeout,
444453
rps_client);
445-
prune_fences = timeout >= 0;
446-
}
447454

448455
dma_fence_put(excl);
449456

450-
/* Oportunistically prune the fences iff we know they have *all* been
457+
/*
458+
* Opportunistically prune the fences iff we know they have *all* been
451459
* signaled and that the reservation object has not been changed (i.e.
452460
* no new fences have been added).
453461
*/

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