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Commit 1734a6e

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torvaldstorvalds
committed
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "A bunch of radeon fixes for oops on module unload, and problems with resetting the dma engine, one nouveau fix for black boxes in rendering on my mbp retina, one sti fix, and a couple of intel fixes" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/nouveau: ltc/gf100-: fix cbc issues on certain boards drm/bochs: add missing drm_connector_register call drm/cirrus: add missing drm_connector_register call drm/radeon: Fix typo 'addr' -> 'entry' in rs400_gart_set_page drm/nouveau/runpm: fix module unload drm/radeon/px: fix module unload vgaswitcheroo: add vga_switcheroo_fini_domain_pm_ops drm/radeon: don't reset dma on r6xx-evergreen init drm/radeon: don't reset sdma on CIK init drm/radeon: don't reset dma on NI/SI init drm/radeon/dpm: fix resume on mullins drm/radeon: Disable HDP flush before every CS again for < r600 drm/radeon: delete unused PTE_* defines drm/i915: Add limited color range readout for HDMI/DP ports on g4x/vlv/chv drm: sti: do not iterate over the info frame array drm/i915: Fix SRC_COPY width on 830/845g
2 parents 46be7b7 + fe3d9c4 commit 1734a6e

25 files changed

+85
-63
lines changed

‎drivers/gpu/drm/bochs/bochs_kms.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,7 @@ static void bochs_connector_init(struct drm_device *dev)
250250
DRM_MODE_CONNECTOR_VIRTUAL);
251251
drm_connector_helper_add(connector,
252252
&bochs_connector_connector_helper_funcs);
253+
drm_connector_register(connector);
253254
}
254255

255256

‎drivers/gpu/drm/cirrus/cirrus_mode.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -555,6 +555,7 @@ static struct drm_connector *cirrus_vga_init(struct drm_device *dev)
555555

556556
drm_connector_helper_add(connector, &cirrus_vga_connector_helper_funcs);
557557

558+
drm_connector_register(connector);
558559
return connector;
559560
}
560561

‎drivers/gpu/drm/i915/intel_dp.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1631,6 +1631,10 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
16311631

16321632
pipe_config->adjusted_mode.flags |= flags;
16331633

1634+
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1635+
tmp & DP_COLOR_RANGE_16_235)
1636+
pipe_config->limited_color_range = true;
1637+
16341638
pipe_config->has_dp_encoder = true;
16351639

16361640
intel_dp_get_m_n(crtc, pipe_config);

‎drivers/gpu/drm/i915/intel_hdmi.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -712,7 +712,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
712712
struct intel_crtc_config *pipe_config)
713713
{
714714
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
715-
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
715+
struct drm_device *dev = encoder->base.dev;
716+
struct drm_i915_private *dev_priv = dev->dev_private;
716717
u32 tmp, flags = 0;
717718
int dotclock;
718719

@@ -734,6 +735,10 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
734735
if (tmp & HDMI_MODE_SELECT_HDMI)
735736
pipe_config->has_audio = true;
736737

738+
if (!HAS_PCH_SPLIT(dev) &&
739+
tmp & HDMI_COLOR_RANGE_16_235)
740+
pipe_config->limited_color_range = true;
741+
737742
pipe_config->adjusted_mode.flags |= flags;
738743

739744
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)

‎drivers/gpu/drm/i915/intel_ringbuffer.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1400,7 +1400,7 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
14001400
*/
14011401
intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
14021402
intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1403-
intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 1024);
1403+
intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
14041404
intel_ring_emit(ring, cs_offset);
14051405
intel_ring_emit(ring, 4096);
14061406
intel_ring_emit(ring, offset);

‎drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,6 @@ nvc0_bar_init(struct nouveau_object *object)
200200

201201
nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
202202
nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
203-
nv_mask(priv, 0x100c80, 0x00000001, 0x00000000);
204203

205204
nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
206205
if (priv->bar[0].mem)

‎drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ nvc0_fb_init(struct nouveau_object *object)
6060

6161
if (priv->r100c10_page)
6262
nv_wr32(priv, 0x100c10, priv->r100c10 >> 8);
63+
nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
6364
return 0;
6465
}
6566

‎drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,7 @@ static int
9898
gf100_ltc_init(struct nouveau_object *object)
9999
{
100100
struct nvkm_ltc_priv *priv = (void *)object;
101+
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
101102
int ret;
102103

103104
ret = nvkm_ltc_init(priv);
@@ -107,6 +108,7 @@ gf100_ltc_init(struct nouveau_object *object)
107108
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
108109
nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
109110
nv_wr32(priv, 0x17e8d4, priv->tag_base);
111+
nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
110112
return 0;
111113
}
112114

‎drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ static int
2828
gk104_ltc_init(struct nouveau_object *object)
2929
{
3030
struct nvkm_ltc_priv *priv = (void *)object;
31+
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
3132
int ret;
3233

3334
ret = nvkm_ltc_init(priv);
@@ -37,6 +38,7 @@ gk104_ltc_init(struct nouveau_object *object)
3738
nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
3839
nv_wr32(priv, 0x17e000, priv->ltc_nr);
3940
nv_wr32(priv, 0x17e8d4, priv->tag_base);
41+
nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
4042
return 0;
4143
}
4244

‎drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,7 @@ static int
9898
gm107_ltc_init(struct nouveau_object *object)
9999
{
100100
struct nvkm_ltc_priv *priv = (void *)object;
101+
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
101102
int ret;
102103

103104
ret = nvkm_ltc_init(priv);
@@ -106,6 +107,7 @@ gm107_ltc_init(struct nouveau_object *object)
106107

107108
nv_wr32(priv, 0x17e27c, priv->ltc_nr);
108109
nv_wr32(priv, 0x17e278, priv->tag_base);
110+
nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
109111
return 0;
110112
}
111113

‎drivers/gpu/drm/nouveau/nouveau_vga.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,16 @@ void
108108
nouveau_vga_fini(struct nouveau_drm *drm)
109109
{
110110
struct drm_device *dev = drm->dev;
111+
bool runtime = false;
112+
113+
if (nouveau_runtime_pm == 1)
114+
runtime = true;
115+
if ((nouveau_runtime_pm == -1) && (nouveau_is_optimus() || nouveau_is_v1_dsm()))
116+
runtime = true;
117+
111118
vga_switcheroo_unregister_client(dev->pdev);
119+
if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())
120+
vga_switcheroo_fini_domain_pm_ops(drm->dev->dev);
112121
vga_client_register(dev->pdev, NULL, NULL, NULL);
113122
}
114123

‎drivers/gpu/drm/radeon/cik_sdma.c

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -489,13 +489,6 @@ int cik_sdma_resume(struct radeon_device *rdev)
489489
{
490490
int r;
491491

492-
/* Reset dma */
493-
WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
494-
RREG32(SRBM_SOFT_RESET);
495-
udelay(50);
496-
WREG32(SRBM_SOFT_RESET, 0);
497-
RREG32(SRBM_SOFT_RESET);
498-
499492
r = cik_sdma_load_microcode(rdev);
500493
if (r)
501494
return r;

‎drivers/gpu/drm/radeon/kv_dpm.c

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,8 @@
3333
#define KV_MINIMUM_ENGINE_CLOCK 800
3434
#define SMC_RAM_END 0x40000
3535

36+
static int kv_enable_nb_dpm(struct radeon_device *rdev,
37+
bool enable);
3638
static void kv_init_graphics_levels(struct radeon_device *rdev);
3739
static int kv_calculate_ds_divider(struct radeon_device *rdev);
3840
static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
@@ -1295,6 +1297,9 @@ void kv_dpm_disable(struct radeon_device *rdev)
12951297
{
12961298
kv_smc_bapm_enable(rdev, false);
12971299

1300+
if (rdev->family == CHIP_MULLINS)
1301+
kv_enable_nb_dpm(rdev, false);
1302+
12981303
/* powerup blocks */
12991304
kv_dpm_powergate_acp(rdev, false);
13001305
kv_dpm_powergate_samu(rdev, false);
@@ -1769,15 +1774,24 @@ static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
17691774
return ret;
17701775
}
17711776

1772-
static int kv_enable_nb_dpm(struct radeon_device *rdev)
1777+
static int kv_enable_nb_dpm(struct radeon_device *rdev,
1778+
bool enable)
17731779
{
17741780
struct kv_power_info *pi = kv_get_pi(rdev);
17751781
int ret = 0;
17761782

1777-
if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1778-
ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1779-
if (ret == 0)
1780-
pi->nb_dpm_enabled = true;
1783+
if (enable) {
1784+
if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1785+
ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1786+
if (ret == 0)
1787+
pi->nb_dpm_enabled = true;
1788+
}
1789+
} else {
1790+
if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1791+
ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable);
1792+
if (ret == 0)
1793+
pi->nb_dpm_enabled = false;
1794+
}
17811795
}
17821796

17831797
return ret;
@@ -1864,7 +1878,7 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
18641878
}
18651879
kv_update_sclk_t(rdev);
18661880
if (rdev->family == CHIP_MULLINS)
1867-
kv_enable_nb_dpm(rdev);
1881+
kv_enable_nb_dpm(rdev, true);
18681882
}
18691883
} else {
18701884
if (pi->enable_dpm) {
@@ -1889,7 +1903,7 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
18891903
}
18901904
kv_update_acp_boot_level(rdev);
18911905
kv_update_sclk_t(rdev);
1892-
kv_enable_nb_dpm(rdev);
1906+
kv_enable_nb_dpm(rdev, true);
18931907
}
18941908
}
18951909

‎drivers/gpu/drm/radeon/ni_dma.c

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -191,12 +191,6 @@ int cayman_dma_resume(struct radeon_device *rdev)
191191
u32 reg_offset, wb_offset;
192192
int i, r;
193193

194-
/* Reset dma */
195-
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
196-
RREG32(SRBM_SOFT_RESET);
197-
udelay(50);
198-
WREG32(SRBM_SOFT_RESET, 0);
199-
200194
for (i = 0; i < 2; i++) {
201195
if (i == 0) {
202196
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

‎drivers/gpu/drm/radeon/r100.c

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -821,6 +821,20 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
821821
return RREG32(RADEON_CRTC2_CRNT_FRAME);
822822
}
823823

824+
/**
825+
* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
826+
* rdev: radeon device structure
827+
* ring: ring buffer struct for emitting packets
828+
*/
829+
static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
830+
{
831+
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
832+
radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
833+
RADEON_HDP_READ_BUFFER_INVALIDATE);
834+
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
835+
radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
836+
}
837+
824838
/* Who ever call radeon_fence_emit should call ring_lock and ask
825839
* for enough space (today caller are ib schedule and buffer move) */
826840
void r100_fence_ring_emit(struct radeon_device *rdev,
@@ -1056,20 +1070,6 @@ void r100_gfx_set_wptr(struct radeon_device *rdev,
10561070
(void)RREG32(RADEON_CP_RB_WPTR);
10571071
}
10581072

1059-
/**
1060-
* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
1061-
* rdev: radeon device structure
1062-
* ring: ring buffer struct for emitting packets
1063-
*/
1064-
void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
1065-
{
1066-
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
1067-
radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
1068-
RADEON_HDP_READ_BUFFER_INVALIDATE);
1069-
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
1070-
radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
1071-
}
1072-
10731073
static void r100_cp_load_microcode(struct radeon_device *rdev)
10741074
{
10751075
const __be32 *fw_data;

‎drivers/gpu/drm/radeon/r600_dma.c

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -124,15 +124,6 @@ int r600_dma_resume(struct radeon_device *rdev)
124124
u32 rb_bufsz;
125125
int r;
126126

127-
/* Reset dma */
128-
if (rdev->family >= CHIP_RV770)
129-
WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
130-
else
131-
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
132-
RREG32(SRBM_SOFT_RESET);
133-
udelay(50);
134-
WREG32(SRBM_SOFT_RESET, 0);
135-
136127
WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
137128
WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
138129

‎drivers/gpu/drm/radeon/r600d.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -44,13 +44,6 @@
4444
#define R6XX_MAX_PIPES 8
4545
#define R6XX_MAX_PIPES_MASK 0xff
4646

47-
/* PTE flags */
48-
#define PTE_VALID (1 << 0)
49-
#define PTE_SYSTEM (1 << 1)
50-
#define PTE_SNOOPED (1 << 2)
51-
#define PTE_READABLE (1 << 5)
52-
#define PTE_WRITEABLE (1 << 6)
53-
5447
/* tiling bits */
5548
#define ARRAY_LINEAR_GENERAL 0x00000000
5649
#define ARRAY_LINEAR_ALIGNED 0x00000001

‎drivers/gpu/drm/radeon/radeon_asic.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -185,7 +185,6 @@ static struct radeon_asic_ring r100_gfx_ring = {
185185
.get_rptr = &r100_gfx_get_rptr,
186186
.get_wptr = &r100_gfx_get_wptr,
187187
.set_wptr = &r100_gfx_set_wptr,
188-
.hdp_flush = &r100_ring_hdp_flush,
189188
};
190189

191190
static struct radeon_asic r100_asic = {
@@ -332,7 +331,6 @@ static struct radeon_asic_ring r300_gfx_ring = {
332331
.get_rptr = &r100_gfx_get_rptr,
333332
.get_wptr = &r100_gfx_get_wptr,
334333
.set_wptr = &r100_gfx_set_wptr,
335-
.hdp_flush = &r100_ring_hdp_flush,
336334
};
337335

338336
static struct radeon_asic r300_asic = {

‎drivers/gpu/drm/radeon/radeon_asic.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -148,8 +148,7 @@ u32 r100_gfx_get_wptr(struct radeon_device *rdev,
148148
struct radeon_ring *ring);
149149
void r100_gfx_set_wptr(struct radeon_device *rdev,
150150
struct radeon_ring *ring);
151-
void r100_ring_hdp_flush(struct radeon_device *rdev,
152-
struct radeon_ring *ring);
151+
153152
/*
154153
* r200,rv250,rs300,rv280
155154
*/

‎drivers/gpu/drm/radeon/radeon_device.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1393,7 +1393,7 @@ int radeon_device_init(struct radeon_device *rdev,
13931393

13941394
r = radeon_init(rdev);
13951395
if (r)
1396-
return r;
1396+
goto failed;
13971397

13981398
r = radeon_ib_ring_tests(rdev);
13991399
if (r)
@@ -1413,7 +1413,7 @@ int radeon_device_init(struct radeon_device *rdev,
14131413
radeon_agp_disable(rdev);
14141414
r = radeon_init(rdev);
14151415
if (r)
1416-
return r;
1416+
goto failed;
14171417
}
14181418

14191419
if ((radeon_testing & 1)) {
@@ -1435,6 +1435,11 @@ int radeon_device_init(struct radeon_device *rdev,
14351435
DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
14361436
}
14371437
return 0;
1438+
1439+
failed:
1440+
if (runtime)
1441+
vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1442+
return r;
14381443
}
14391444

14401445
static void radeon_debugfs_remove_files(struct radeon_device *rdev);
@@ -1455,6 +1460,8 @@ void radeon_device_fini(struct radeon_device *rdev)
14551460
radeon_bo_evict_vram(rdev);
14561461
radeon_fini(rdev);
14571462
vga_switcheroo_unregister_client(rdev->pdev);
1463+
if (rdev->flags & RADEON_IS_PX)
1464+
vga_switcheroo_fini_domain_pm_ops(rdev->dev);
14581465
vga_client_register(rdev->pdev, NULL, NULL, NULL);
14591466
if (rdev->rio_mem)
14601467
pci_iounmap(rdev->pdev, rdev->rio_mem);

‎drivers/gpu/drm/radeon/radeon_drv.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@
8383
* CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
8484
* 2.39.0 - Add INFO query for number of active CUs
8585
* 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
86-
* CS to GPU
86+
* CS to GPU on >= r600
8787
*/
8888
#define KMS_DRIVER_MAJOR 2
8989
#define KMS_DRIVER_MINOR 40

‎drivers/gpu/drm/radeon/rs400.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -221,9 +221,9 @@ void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
221221
entry = (lower_32_bits(addr) & PAGE_MASK) |
222222
((upper_32_bits(addr) & 0xff) << 4);
223223
if (flags & RADEON_GART_PAGE_READ)
224-
addr |= RS400_PTE_READABLE;
224+
entry |= RS400_PTE_READABLE;
225225
if (flags & RADEON_GART_PAGE_WRITE)
226-
addr |= RS400_PTE_WRITEABLE;
226+
entry |= RS400_PTE_WRITEABLE;
227227
if (!(flags & RADEON_GART_PAGE_SNOOP))
228228
entry |= RS400_PTE_UNSNOOPED;
229229
entry = cpu_to_le32(entry);

‎drivers/gpu/drm/sti/sti_hdmi.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,6 @@ static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
298298
hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD2(HDMI_IFRAME_SLOT_AVI));
299299

300300
val = frame[0xC];
301-
val |= frame[0xD] << 8;
302301
hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD3(HDMI_IFRAME_SLOT_AVI));
303302

304303
/* Enable transmission slot for AVI infoframe

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