|
288 | 288 | #size-cells = <0>;
|
289 | 289 | clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
|
290 | 290 | clock-names = "biu", "ciu";
|
| 291 | + assigned-clocks = |
| 292 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, |
| 293 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, |
| 294 | + <&clock_top TOP_SCLK_MMC0>; |
| 295 | + assigned-clock-parents = |
| 296 | + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, |
| 297 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; |
| 298 | + assigned-clock-rates = <0>, <0>, <800000000>; |
291 | 299 | fifo-depth = <64>;
|
292 | 300 | status = "disabled";
|
293 | 301 | };
|
|
300 | 308 | #size-cells = <0>;
|
301 | 309 | clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
|
302 | 310 | clock-names = "biu", "ciu";
|
| 311 | + assigned-clocks = |
| 312 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, |
| 313 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, |
| 314 | + <&clock_top TOP_SCLK_MMC1>; |
| 315 | + assigned-clock-parents = |
| 316 | + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, |
| 317 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; |
| 318 | + assigned-clock-rates = <0>, <0>, <800000000>; |
303 | 319 | fifo-depth = <64>;
|
304 | 320 | status = "disabled";
|
305 | 321 | };
|
|
312 | 328 | #size-cells = <0>;
|
313 | 329 | clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
|
314 | 330 | clock-names = "biu", "ciu";
|
| 331 | + assigned-clocks = |
| 332 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, |
| 333 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, |
| 334 | + <&clock_top TOP_SCLK_MMC2>; |
| 335 | + assigned-clock-parents = |
| 336 | + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, |
| 337 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; |
| 338 | + assigned-clock-rates = <0>, <0>, <800000000>; |
315 | 339 | fifo-depth = <64>;
|
316 | 340 | status = "disabled";
|
317 | 341 | };
|
|
0 commit comments