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torvaldstorvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "This updated pull request does not contain the last few GIC related patches which were reported to cause a regression. There is a fix available, but I let it breed for a couple of days first. The irq departement provides: - new infrastructure to support non PCI based MSI interrupts - a couple of new irq chip drivers - the usual pile of fixlets and updates to irq chip drivers - preparatory changes for removal of the irq argument from interrupt flow handlers - preparatory changes to remove IRQF_VALID" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (129 commits) irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sources irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2 irqchip: Add documentation for the bcm2836 interrupt controller irqchip/bcm2835: Add support for being used as a second level controller irqchip/bcm2835: Refactor handle_IRQ() calls out of MAKE_HWIRQ PCI: xilinx: Fix typo in function name irqchip/gic: Ensure gic_cpu_if_up/down() programs correct GIC instance irqchip/gic: Only allow the primary GIC to set the CPU map PCI/MSI: pci-xgene-msi: Consolidate chained IRQ handler install/remove unicore32/irq: Prepare puv3_gpio_handler for irq argument removal tile/pci_gx: Prepare trio_handle_level_irq for irq argument removal m68k/irq: Prepare irq handlers for irq argument removal C6X/megamode-pic: Prepare megamod_irq_cascade for irq argument removal blackfin: Prepare irq handlers for irq argument removal arc/irq: Prepare idu_cascade_isr for irq argument removal sparc/irq: Use access helper irq_data_get_affinity_mask() sparc/irq: Use helper irq_data_get_irq_handler_data() parisc/irq: Use access helper irq_data_get_affinity_mask() mn10300/irq: Use access helper irq_data_get_affinity_mask() irqchip/i8259: Prepare i8259_irq_dispatch for irq argument removal ...
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‎Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,14 @@ The BCM2835 contains a custom top-level interrupt controller, which supports
55
controller, or the HW block containing it, is referred to occasionally
66
as "armctrl" in the SoC documentation, hence naming of this binding.
77

8+
The BCM2836 contains the same interrupt controller with the same
9+
interrupts, but the per-CPU interrupt controller is the root, and an
10+
interrupt there indicates that the ARMCTRL has an interrupt to handle.
11+
812
Required properties:
913

10-
- compatible : should be "brcm,bcm2835-armctrl-ic"
14+
- compatible : should be "brcm,bcm2835-armctrl-ic" or
15+
"brcm,bcm2836-armctrl-ic"
1116
- reg : Specifies base physical address and size of the registers.
1217
- interrupt-controller : Identifies the node as an interrupt controller
1318
- #interrupt-cells : Specifies the number of cells needed to encode an
@@ -20,6 +25,12 @@ Required properties:
2025
The 2nd cell contains the interrupt number within the bank. Valid values
2126
are 0..7 for bank 0, and 0..31 for bank 1.
2227

28+
Additional required properties for brcm,bcm2836-armctrl-ic:
29+
- interrupt-parent : Specifies the parent interrupt controller when this
30+
controller is the second level.
31+
- interrupts : Specifies the interrupt on the parent for this interrupt
32+
controller to handle.
33+
2334
The interrupt sources are as follows:
2435

2536
Bank 0:
@@ -102,9 +113,21 @@ Bank 2:
102113

103114
Example:
104115

116+
/* BCM2835, first level */
105117
intc: interrupt-controller {
106118
compatible = "brcm,bcm2835-armctrl-ic";
107119
reg = <0x7e00b200 0x200>;
108120
interrupt-controller;
109121
#interrupt-cells = <2>;
110122
};
123+
124+
/* BCM2836, second level */
125+
intc: interrupt-controller {
126+
compatible = "brcm,bcm2836-armctrl-ic";
127+
reg = <0x7e00b200 0x200>;
128+
interrupt-controller;
129+
#interrupt-cells = <2>;
130+
131+
interrupt-parent = <&local_intc>;
132+
interrupts = <8>;
133+
};

‎Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
BCM2836 per-CPU interrupt controller
2+
3+
The BCM2836 has a per-cpu interrupt controller for the timer, PMU
4+
events, and SMP IPIs. One of the CPUs may receive interrupts for the
5+
peripheral (GPU) events, which chain to the BCM2835-style interrupt
6+
controller.
7+
8+
Required properties:
9+
10+
- compatible: Should be "brcm,bcm2836-l1-intc"
11+
- reg: Specifies base physical address and size of the
12+
registers
13+
- interrupt-controller: Identifies the node as an interrupt controller
14+
- #interrupt-cells: Specifies the number of cells needed to encode an
15+
interrupt source. The value shall be 1
16+
17+
Please refer to interrupts.txt in this directory for details of the common
18+
Interrupt Controllers bindings used by client devices.
19+
20+
The interrupt sources are as follows:
21+
22+
0: CNTPSIRQ
23+
1: CNTPNSIRQ
24+
2: CNTHPIRQ
25+
3: CNTVIRQ
26+
8: GPU_FAST
27+
9: PMU_FAST
28+
29+
Example:
30+
31+
local_intc: local_intc {
32+
compatible = "brcm,bcm2836-l1-intc";
33+
reg = <0x40000000 0x100>;
34+
interrupt-controller;
35+
#interrupt-cells = <1>;
36+
interrupt-parent = <&local_intc>;
37+
};

‎arch/alpha/kernel/irq.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ int irq_select_affinity(unsigned int irq)
5959
cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
6060
last_cpu = cpu;
6161

62-
cpumask_copy(data->affinity, cpumask_of(cpu));
62+
cpumask_copy(irq_data_get_affinity_mask(data), cpumask_of(cpu));
6363
chip->irq_set_affinity(data, cpumask_of(cpu), false);
6464
return 0;
6565
}

‎arch/arc/kernel/mcip.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -252,9 +252,10 @@ static struct irq_chip idu_irq_chip = {
252252

253253
static int idu_first_irq;
254254

255-
static void idu_cascade_isr(unsigned int core_irq, struct irq_desc *desc)
255+
static void idu_cascade_isr(unsigned int __core_irq, struct irq_desc *desc)
256256
{
257257
struct irq_domain *domain = irq_desc_get_handler_data(desc);
258+
unsigned int core_irq = irq_desc_get_irq(desc);
258259
unsigned int idu_irq;
259260

260261
idu_irq = core_irq - idu_first_irq;

‎arch/arm/mach-shmobile/setup-r8a7779.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,6 @@ static void __init r8a7779_map_io(void)
6262

6363
static void __init r8a7779_init_irq_dt(void)
6464
{
65-
gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
66-
6765
irqchip_init();
6866

6967
/* route all interrupts to ARM */

‎arch/arm/mach-ux500/cpu.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,6 @@ void __init ux500_init_irq(void)
5656
struct device_node *np;
5757
struct resource r;
5858

59-
gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
6059
irqchip_init();
6160
np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
6261
of_address_to_resource(np, 0, &r);

‎arch/arm/mach-vexpress/tc2_pm.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
8080
* to the CPU by disabling the GIC CPU IF to prevent wfi
8181
* from completing execution behind power controller back
8282
*/
83-
gic_cpu_if_down();
83+
gic_cpu_if_down(0);
8484
}
8585

8686
static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster)

‎arch/arm/mach-zynq/common.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,6 @@ static void __init zynq_map_io(void)
186186

187187
static void __init zynq_irq_init(void)
188188
{
189-
gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
190189
irqchip_init();
191190
}
192191

‎arch/avr32/mach-at32ap/extint.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -128,9 +128,9 @@ static int eic_set_irq_type(struct irq_data *d, unsigned int flow_type)
128128

129129
irqd_set_trigger_type(d, flow_type);
130130
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
131-
__irq_set_handler_locked(irq, handle_level_irq);
131+
irq_set_handler_locked(d, handle_level_irq);
132132
else
133-
__irq_set_handler_locked(irq, handle_edge_irq);
133+
irq_set_handler_locked(d, handle_edge_irq);
134134

135135
return IRQ_SET_MASK_OK_NOCOPY;
136136
}

‎arch/avr32/mach-at32ap/pio.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -286,7 +286,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
286286
struct pio_device *pio = irq_desc_get_chip_data(desc);
287287
unsigned gpio_irq;
288288

289-
gpio_irq = (unsigned) irq_get_handler_data(irq);
289+
gpio_irq = (unsigned) irq_desc_get_handler_data(desc);
290290
for (;;) {
291291
u32 isr;
292292

@@ -312,15 +312,15 @@ gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq)
312312
unsigned i;
313313

314314
irq_set_chip_data(irq, pio);
315-
irq_set_handler_data(irq, (void *)gpio_irq);
316315

317316
for (i = 0; i < 32; i++, gpio_irq++) {
318317
irq_set_chip_data(gpio_irq, pio);
319318
irq_set_chip_and_handler(gpio_irq, &gpio_irqchip,
320319
handle_simple_irq);
321320
}
322321

323-
irq_set_chained_handler(irq, gpio_irq_handler);
322+
irq_set_chained_handler_and_data(irq, gpio_irq_handler,
323+
(void *)gpio_irq);
324324
}
325325

326326
/*--------------------------------------------------------------------------*/

‎arch/blackfin/mach-bf537/ints-priority.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,9 +182,11 @@ static struct irq_chip bf537_mac_rx_irqchip = {
182182
.irq_unmask = bf537_mac_rx_unmask_irq,
183183
};
184184

185-
static void bf537_demux_mac_rx_irq(unsigned int int_irq,
185+
static void bf537_demux_mac_rx_irq(unsigned int __int_irq,
186186
struct irq_desc *desc)
187187
{
188+
unsigned int int_irq = irq_desc_get_irq(desc);
189+
188190
if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
189191
bfin_handle_irq(IRQ_MAC_RX);
190192
else

‎arch/blackfin/mach-common/ints-priority.c

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,8 @@ void bfin_internal_unmask_irq(unsigned int irq)
194194
#ifdef CONFIG_SMP
195195
static void bfin_internal_unmask_irq_chip(struct irq_data *d)
196196
{
197-
bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
197+
bfin_internal_unmask_irq_affinity(d->irq,
198+
irq_data_get_affinity_mask(d));
198199
}
199200

200201
static int bfin_internal_set_affinity(struct irq_data *d,
@@ -685,12 +686,12 @@ void bfin_demux_mac_status_irq(unsigned int int_err_irq,
685686
}
686687
#endif
687688

688-
static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
689+
static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle)
689690
{
690691
#ifdef CONFIG_IPIPE
691692
handle = handle_level_irq;
692693
#endif
693-
__irq_set_handler_locked(irq, handle);
694+
irq_set_handler_locked(d, handle);
694695
}
695696

696697
#ifdef CONFIG_GPIO_ADI
@@ -802,9 +803,9 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
802803
}
803804

804805
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
805-
bfin_set_irq_handler(irq, handle_edge_irq);
806+
bfin_set_irq_handler(d, handle_edge_irq);
806807
else
807-
bfin_set_irq_handler(irq, handle_level_irq);
808+
bfin_set_irq_handler(d, handle_level_irq);
808809

809810
return 0;
810811
}
@@ -824,9 +825,9 @@ static void bfin_demux_gpio_block(unsigned int irq)
824825
}
825826
}
826827

827-
void bfin_demux_gpio_irq(unsigned int inta_irq,
828-
struct irq_desc *desc)
828+
void bfin_demux_gpio_irq(unsigned int __inta_irq, struct irq_desc *desc)
829829
{
830+
unsigned int inta_irq = irq_desc_get_irq(desc);
830831
unsigned int irq;
831832

832833
switch (inta_irq) {

‎arch/c6x/platforms/megamod-pic.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -93,10 +93,11 @@ static struct irq_chip megamod_chip = {
9393
.irq_unmask = unmask_megamod,
9494
};
9595

96-
static void megamod_irq_cascade(unsigned int irq, struct irq_desc *desc)
96+
static void megamod_irq_cascade(unsigned int __irq, struct irq_desc *desc)
9797
{
9898
struct megamod_cascade_data *cascade;
9999
struct megamod_pic *pic;
100+
unsigned int irq;
100101
u32 events;
101102
int n, idx;
102103

@@ -282,8 +283,8 @@ static struct megamod_pic * __init init_megamod_pic(struct device_node *np)
282283
soc_writel(~0, &pic->regs->evtmask[i]);
283284
soc_writel(~0, &pic->regs->evtclr[i]);
284285

285-
irq_set_handler_data(irq, &cascade_data[i]);
286-
irq_set_chained_handler(irq, megamod_irq_cascade);
286+
irq_set_chained_handler_and_data(irq, megamod_irq_cascade,
287+
&cascade_data[i]);
287288
}
288289

289290
/* Finally, set up the MUX registers */

‎arch/ia64/kernel/iosapic.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -610,9 +610,9 @@ register_intr (unsigned int gsi, int irq, unsigned char delivery,
610610
chip->name, irq_type->name);
611611
chip = irq_type;
612612
}
613-
__irq_set_chip_handler_name_locked(irq, chip, trigger == IOSAPIC_EDGE ?
614-
handle_edge_irq : handle_level_irq,
615-
NULL);
613+
irq_set_chip_handler_name_locked(irq_get_irq_data(irq), chip,
614+
trigger == IOSAPIC_EDGE ? handle_edge_irq : handle_level_irq,
615+
NULL);
616616
return 0;
617617
}
618618

@@ -838,7 +838,7 @@ iosapic_unregister_intr (unsigned int gsi)
838838
if (iosapic_intr_info[irq].count == 0) {
839839
#ifdef CONFIG_SMP
840840
/* Clear affinity */
841-
cpumask_setall(irq_get_irq_data(irq)->affinity);
841+
cpumask_setall(irq_get_affinity_mask(irq));
842842
#endif
843843
/* Clear the interrupt information */
844844
iosapic_intr_info[irq].dest = 0;

‎arch/ia64/kernel/irq.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
6767
void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
6868
{
6969
if (irq < NR_IRQS) {
70-
cpumask_copy(irq_get_irq_data(irq)->affinity,
70+
cpumask_copy(irq_get_affinity_mask(irq),
7171
cpumask_of(cpu_logical_id(hwid)));
7272
irq_redir[irq] = (char) (redir & 0xff);
7373
}
@@ -119,8 +119,8 @@ static void migrate_irqs(void)
119119
if (irqd_is_per_cpu(data))
120120
continue;
121121

122-
if (cpumask_any_and(data->affinity, cpu_online_mask)
123-
>= nr_cpu_ids) {
122+
if (cpumask_any_and(irq_data_get_affinity_mask(data),
123+
cpu_online_mask) >= nr_cpu_ids) {
124124
/*
125125
* Save it for phase 2 processing
126126
*/

‎arch/ia64/kernel/msi_ia64.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata,
2323
if (irq_prepare_move(irq, cpu))
2424
return -1;
2525

26-
__get_cached_msi_msg(idata->msi_desc, &msg);
26+
__get_cached_msi_msg(irq_data_get_msi_desc(idata), &msg);
2727

2828
addr = msg.address_lo;
2929
addr &= MSI_ADDR_DEST_ID_MASK;
@@ -36,7 +36,7 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata,
3636
msg.data = data;
3737

3838
pci_write_msi_msg(irq, &msg);
39-
cpumask_copy(idata->affinity, cpumask_of(cpu));
39+
cpumask_copy(irq_data_get_affinity_mask(idata), cpumask_of(cpu));
4040

4141
return 0;
4242
}
@@ -148,7 +148,7 @@ static int dmar_msi_set_affinity(struct irq_data *data,
148148
msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu));
149149

150150
dmar_msi_write(irq, &msg);
151-
cpumask_copy(data->affinity, mask);
151+
cpumask_copy(irq_data_get_affinity_mask(data), mask);
152152

153153
return 0;
154154
}

‎arch/ia64/sn/kernel/msi_sn.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -175,7 +175,7 @@ static int sn_set_msi_irq_affinity(struct irq_data *data,
175175
* Release XIO resources for the old MSI PCI address
176176
*/
177177

178-
__get_cached_msi_msg(data->msi_desc, &msg);
178+
__get_cached_msi_msg(irq_data_get_msi_desc(data), &msg);
179179
sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
180180
pdev = sn_pdev->pdi_linux_pcidev;
181181
provider = SN_PCIDEV_BUSPROVIDER(pdev);
@@ -206,7 +206,7 @@ static int sn_set_msi_irq_affinity(struct irq_data *data,
206206
msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
207207

208208
pci_write_msi_msg(irq, &msg);
209-
cpumask_copy(data->affinity, cpu_mask);
209+
cpumask_copy(irq_data_get_affinity_mask(data), cpu_mask);
210210

211211
return 0;
212212
}

‎arch/m68k/coldfire/intc-5272.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,8 +143,10 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
143143
* We need to be careful with the masking/acking due to the side effects
144144
* of masking an interrupt.
145145
*/
146-
static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
146+
static void intc_external_irq(unsigned int __irq, struct irq_desc *desc)
147147
{
148+
unsigned int irq = irq_desc_get_irq(desc);
149+
148150
irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
149151
handle_simple_irq(irq, desc);
150152
}

‎arch/m68k/mac/oss.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -63,13 +63,15 @@ void __init oss_nubus_init(void)
6363
* Handle miscellaneous OSS interrupts.
6464
*/
6565

66-
static void oss_irq(unsigned int irq, struct irq_desc *desc)
66+
static void oss_irq(unsigned int __irq, struct irq_desc *desc)
6767
{
6868
int events = oss->irq_pending &
69-
(OSS_IP_IOPSCC | OSS_IP_SCSI | OSS_IP_IOPISM);
69+
(OSS_IP_IOPSCC | OSS_IP_SCSI | OSS_IP_IOPISM);
7070

7171
#ifdef DEBUG_IRQS
7272
if ((console_loglevel == 10) && !(events & OSS_IP_SCSI)) {
73+
unsigned int irq = irq_desc_get_irq(desc);
74+
7375
printk("oss_irq: irq %u events = 0x%04X\n", irq,
7476
(int) oss->irq_pending);
7577
}

‎arch/m68k/mac/psc.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -113,9 +113,10 @@ void __init psc_init(void)
113113
* PSC interrupt handler. It's a lot like the VIA interrupt handler.
114114
*/
115115

116-
static void psc_irq(unsigned int irq, struct irq_desc *desc)
116+
static void psc_irq(unsigned int __irq, struct irq_desc *desc)
117117
{
118118
unsigned int offset = (unsigned int)irq_desc_get_handler_data(desc);
119+
unsigned int irq = irq_desc_get_irq(desc);
119120
int pIFR = pIFRbase + offset;
120121
int pIER = pIERbase + offset;
121122
int irq_num;

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