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Merge tag 'iommu-updates-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel: - PASID table handling updates for the Intel VT-d driver. It implements a global PASID space now so that applications usings multiple devices will just have one PASID. - A new config option to make iommu passthroug mode the default. - New sysfs attribute for iommu groups to export the type of the default domain. - A debugfs interface (for debug only) usable by IOMMU drivers to export internals to user-space. - R-Car Gen3 SoCs support for the ipmmu-vmsa driver - The ARM-SMMU now aborts transactions from unknown devices and devices not attached to any domain. - Various cleanups and smaller fixes all over the place. * tag 'iommu-updates-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (42 commits) iommu/omap: Fix cache flushes on L2 table entries iommu: Remove the ->map_sg indirection iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel iommu/arm-smmu-v3: Prevent any devices access to memory without registration iommu/ipmmu-vmsa: Don't register as BUS IOMMU if machine doesn't have IPMMU-VMSA iommu/ipmmu-vmsa: Clarify supported platforms iommu/ipmmu-vmsa: Fix allocation in atomic context iommu: Add config option to set passthrough as default iommu: Add sysfs attribyte for domain type iommu/arm-smmu-v3: sync the OVACKFLG to PRIQ consumer register iommu/arm-smmu: Error out only if not enough context interrupts iommu/io-pgtable-arm-v7s: Abort allocation when table address overflows the PTE iommu/io-pgtable-arm: Fix pgtable allocation in selftest iommu/vt-d: Remove the obsolete per iommu pasid tables iommu/vt-d: Apply per pci device pasid table in SVA iommu/vt-d: Allocate and free pasid table iommu/vt-d: Per PCI device pasid table interfaces iommu/vt-d: Add for_each_device_domain() helper iommu/vt-d: Move device_domain_info to header iommu/vt-d: Apply global PASID in SVA ...
2 parents d972604 + 6488a7f commit 18b8bfd

36 files changed

+839
-277
lines changed

Documentation/admin-guide/kernel-parameters.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1744,7 +1744,8 @@
17441744
merge
17451745
nomerge
17461746
soft
1747-
pt [x86, IA-64]
1747+
pt [x86]
1748+
nopt [x86]
17481749
nobypass [PPC/POWERNV]
17491750
Disable IOMMU bypass, using IOMMU for PCI devices.
17501751

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,10 @@ Required Properties:
1919
- "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
2020
- "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
2121
- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
22+
- "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU.
2223
- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
24+
- "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU.
25+
- "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU.
2326
- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
2427
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
2528
IPMMU.

arch/x86/include/asm/irq_remapping.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,11 @@ enum irq_remap_cap {
3333
IRQ_POSTING_CAP = 0,
3434
};
3535

36+
enum {
37+
IRQ_REMAP_XAPIC_MODE,
38+
IRQ_REMAP_X2APIC_MODE,
39+
};
40+
3641
struct vcpu_data {
3742
u64 pi_desc_addr; /* Physical address of PI Descriptor */
3843
u32 vector; /* Guest vector of the interrupt */

arch/x86/kernel/pci-dma.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,8 +40,14 @@ int iommu_detected __read_mostly = 0;
4040
* devices and allow every device to access to whole physical memory. This is
4141
* useful if a user wants to use an IOMMU only for KVM device assignment to
4242
* guests and not for driver dma translation.
43+
* It is also possible to disable by default in kernel config, and enable with
44+
* iommu=nopt at boot time.
4345
*/
46+
#ifdef CONFIG_IOMMU_DEFAULT_PASSTHROUGH
47+
int iommu_pass_through __read_mostly = 1;
48+
#else
4449
int iommu_pass_through __read_mostly;
50+
#endif
4551

4652
extern struct iommu_table_entry __iommu_table[], __iommu_table_end[];
4753

@@ -135,6 +141,8 @@ static __init int iommu_setup(char *p)
135141
#endif
136142
if (!strncmp(p, "pt", 2))
137143
iommu_pass_through = 1;
144+
if (!strncmp(p, "nopt", 4))
145+
iommu_pass_through = 0;
138146

139147
gart_parse_options(p);
140148

drivers/iommu/Kconfig

Lines changed: 35 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,27 @@ config IOMMU_IO_PGTABLE_ARMV7S_SELFTEST
6060

6161
endmenu
6262

63+
config IOMMU_DEBUGFS
64+
bool "Export IOMMU internals in DebugFS"
65+
depends on DEBUG_FS
66+
help
67+
Allows exposure of IOMMU device internals. This option enables
68+
the use of debugfs by IOMMU drivers as required. Devices can,
69+
at initialization time, cause the IOMMU code to create a top-level
70+
debug/iommu directory, and then populate a subdirectory with
71+
entries as required.
72+
73+
config IOMMU_DEFAULT_PASSTHROUGH
74+
bool "IOMMU passthrough by default"
75+
depends on IOMMU_API
76+
help
77+
Enable passthrough by default, removing the need to pass in
78+
iommu.passthrough=on or iommu=pt through command line. If this
79+
is enabled, you can still disable with iommu.passthrough=off
80+
or iommu=nopt depending on the architecture.
81+
82+
If unsure, say N here.
83+
6384
config IOMMU_IOVA
6485
tristate
6586

@@ -135,6 +156,18 @@ config AMD_IOMMU_V2
135156
hardware. Select this option if you want to use devices that support
136157
the PCI PRI and PASID interface.
137158

159+
config AMD_IOMMU_DEBUGFS
160+
bool "Enable AMD IOMMU internals in DebugFS"
161+
depends on AMD_IOMMU && IOMMU_DEBUGFS
162+
---help---
163+
!!!WARNING!!! !!!WARNING!!! !!!WARNING!!! !!!WARNING!!!
164+
165+
DO NOT ENABLE THIS OPTION UNLESS YOU REALLY, -REALLY- KNOW WHAT YOU ARE DOING!!!
166+
Exposes AMD IOMMU device internals in DebugFS.
167+
168+
This option is -NOT- intended for production environments, and should
169+
not generally be enabled.
170+
138171
# Intel IOMMU support
139172
config DMAR_TABLE
140173
bool
@@ -284,8 +317,8 @@ config IPMMU_VMSA
284317
select IOMMU_IO_PGTABLE_LPAE
285318
select ARM_DMA_USE_IOMMU
286319
help
287-
Support for the Renesas VMSA-compatible IPMMU Renesas found in the
288-
R-Mobile APE6 and R-Car H2/M2 SoCs.
320+
Support for the Renesas VMSA-compatible IPMMU found in the R-Mobile
321+
APE6, R-Car Gen2, and R-Car Gen3 SoCs.
289322

290323
If unsure, say N.
291324

drivers/iommu/Makefile

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
obj-$(CONFIG_IOMMU_API) += iommu.o
33
obj-$(CONFIG_IOMMU_API) += iommu-traces.o
44
obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
5+
obj-$(CONFIG_IOMMU_DEBUGFS) += iommu-debugfs.o
56
obj-$(CONFIG_IOMMU_DMA) += dma-iommu.o
67
obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o
78
obj-$(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) += io-pgtable-arm-v7s.o
@@ -10,11 +11,12 @@ obj-$(CONFIG_IOMMU_IOVA) += iova.o
1011
obj-$(CONFIG_OF_IOMMU) += of_iommu.o
1112
obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o
1213
obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o
14+
obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += amd_iommu_debugfs.o
1315
obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o
1416
obj-$(CONFIG_ARM_SMMU) += arm-smmu.o
1517
obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o
1618
obj-$(CONFIG_DMAR_TABLE) += dmar.o
17-
obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o
19+
obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o intel-pasid.o
1820
obj-$(CONFIG_INTEL_IOMMU_SVM) += intel-svm.o
1921
obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
2022
obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o

drivers/iommu/amd_iommu.c

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1404,6 +1404,8 @@ static u64 *fetch_pte(struct protection_domain *domain,
14041404
int level;
14051405
u64 *pte;
14061406

1407+
*page_size = 0;
1408+
14071409
if (address > PM_LEVEL_SIZE(domain->mode))
14081410
return NULL;
14091411

@@ -1944,12 +1946,6 @@ static int __attach_device(struct iommu_dev_data *dev_data,
19441946
{
19451947
int ret;
19461948

1947-
/*
1948-
* Must be called with IRQs disabled. Warn here to detect early
1949-
* when its not.
1950-
*/
1951-
WARN_ON(!irqs_disabled());
1952-
19531949
/* lock domain */
19541950
spin_lock(&domain->lock);
19551951

@@ -2115,12 +2111,6 @@ static void __detach_device(struct iommu_dev_data *dev_data)
21152111
{
21162112
struct protection_domain *domain;
21172113

2118-
/*
2119-
* Must be called with IRQs disabled. Warn here to detect early
2120-
* when its not.
2121-
*/
2122-
WARN_ON(!irqs_disabled());
2123-
21242114
domain = dev_data->domain;
21252115

21262116
spin_lock(&domain->lock);
@@ -2405,9 +2395,9 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
24052395
}
24062396

24072397
if (amd_iommu_unmap_flush) {
2408-
dma_ops_free_iova(dma_dom, dma_addr, pages);
24092398
domain_flush_tlb(&dma_dom->domain);
24102399
domain_flush_complete(&dma_dom->domain);
2400+
dma_ops_free_iova(dma_dom, dma_addr, pages);
24112401
} else {
24122402
pages = __roundup_pow_of_two(pages);
24132403
queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
@@ -3192,7 +3182,6 @@ const struct iommu_ops amd_iommu_ops = {
31923182
.detach_dev = amd_iommu_detach_device,
31933183
.map = amd_iommu_map,
31943184
.unmap = amd_iommu_unmap,
3195-
.map_sg = default_iommu_map_sg,
31963185
.iova_to_phys = amd_iommu_iova_to_phys,
31973186
.add_device = amd_iommu_add_device,
31983187
.remove_device = amd_iommu_remove_device,
@@ -3874,7 +3863,8 @@ static void irte_ga_prepare(void *entry,
38743863
irte->lo.fields_remap.int_type = delivery_mode;
38753864
irte->lo.fields_remap.dm = dest_mode;
38763865
irte->hi.fields.vector = vector;
3877-
irte->lo.fields_remap.destination = dest_apicid;
3866+
irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3867+
irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
38783868
irte->lo.fields_remap.valid = 1;
38793869
}
38803870

@@ -3927,7 +3917,10 @@ static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
39273917

39283918
if (!irte->lo.fields_remap.guest_mode) {
39293919
irte->hi.fields.vector = vector;
3930-
irte->lo.fields_remap.destination = dest_apicid;
3920+
irte->lo.fields_remap.destination =
3921+
APICID_TO_IRTE_DEST_LO(dest_apicid);
3922+
irte->hi.fields.destination =
3923+
APICID_TO_IRTE_DEST_HI(dest_apicid);
39313924
modify_irte_ga(devid, index, irte, NULL);
39323925
}
39333926
}
@@ -4344,7 +4337,10 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
43444337
irte->lo.val = 0;
43454338
irte->hi.fields.vector = cfg->vector;
43464339
irte->lo.fields_remap.guest_mode = 0;
4347-
irte->lo.fields_remap.destination = cfg->dest_apicid;
4340+
irte->lo.fields_remap.destination =
4341+
APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4342+
irte->hi.fields.destination =
4343+
APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
43484344
irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
43494345
irte->lo.fields_remap.dm = apic->irq_dest_mode;
43504346

@@ -4461,8 +4457,12 @@ int amd_iommu_update_ga(int cpu, bool is_run, void *data)
44614457
raw_spin_lock_irqsave(&table->lock, flags);
44624458

44634459
if (ref->lo.fields_vapic.guest_mode) {
4464-
if (cpu >= 0)
4465-
ref->lo.fields_vapic.destination = cpu;
4460+
if (cpu >= 0) {
4461+
ref->lo.fields_vapic.destination =
4462+
APICID_TO_IRTE_DEST_LO(cpu);
4463+
ref->hi.fields.destination =
4464+
APICID_TO_IRTE_DEST_HI(cpu);
4465+
}
44664466
ref->lo.fields_vapic.is_run = is_run;
44674467
barrier();
44684468
}

drivers/iommu/amd_iommu_debugfs.c

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* AMD IOMMU driver
4+
*
5+
* Copyright (C) 2018 Advanced Micro Devices, Inc.
6+
*
7+
* Author: Gary R Hook <[email protected]>
8+
*/
9+
10+
#include <linux/debugfs.h>
11+
#include <linux/iommu.h>
12+
#include <linux/pci.h>
13+
#include "amd_iommu_proto.h"
14+
#include "amd_iommu_types.h"
15+
16+
static struct dentry *amd_iommu_debugfs;
17+
static DEFINE_MUTEX(amd_iommu_debugfs_lock);
18+
19+
#define MAX_NAME_LEN 20
20+
21+
void amd_iommu_debugfs_setup(struct amd_iommu *iommu)
22+
{
23+
char name[MAX_NAME_LEN + 1];
24+
25+
mutex_lock(&amd_iommu_debugfs_lock);
26+
if (!amd_iommu_debugfs)
27+
amd_iommu_debugfs = debugfs_create_dir("amd",
28+
iommu_debugfs_dir);
29+
mutex_unlock(&amd_iommu_debugfs_lock);
30+
31+
snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index);
32+
iommu->debugfs = debugfs_create_dir(name, amd_iommu_debugfs);
33+
}

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