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Merge tag 'dmaengine-4.17-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul: "This time we have couple of new drivers along with updates to drivers: - new drivers for the DesignWare AXI DMAC and MediaTek High-Speed DMA controllers - stm32 dma and qcom bam dma driver updates - norandom test option for dmatest" * tag 'dmaengine-4.17-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (30 commits) dmaengine: stm32-dma: properly mask irq bits dmaengine: stm32-dma: fix max items per transfer dmaengine: stm32-dma: fix DMA IRQ status handling dmaengine: stm32-dma: Improve memory burst management dmaengine: stm32-dma: fix typo and reported checkpatch warnings dmaengine: stm32-dma: fix incomplete configuration in cyclic mode dmaengine: stm32-dma: threshold manages with bitfield feature dt-bindings: stm32-dma: introduce DMA features bitfield dt-bindings: rcar-dmac: Document r8a77470 support dmaengine: rcar-dmac: Fix too early/late system suspend/resume callbacks dmaengine: dw-axi-dmac: fix spelling mistake: "catched" -> "caught" dmaengine: edma: Check the memory allocation for the memcpy dma device dmaengine: at_xdmac: fix rare residue corruption dmaengine: mediatek: update MAINTAINERS entry with MediaTek DMA driver dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC dt-bindings: dmaengine: Add MediaTek High-Speed DMA controller bindings dt-bindings: Document the Synopsys DW AXI DMA bindings dmaengine: Introduce DW AXI DMAC driver dmaengine: pl330: fix a race condition in case of threaded irqs dmaengine: imx-sdma: fix pagefault when channel is disabled during interrupt ...
2 parents 92589cb + 2ffb850 commit 1b02dcb

24 files changed

+2871
-74
lines changed

‎Documentation/devicetree/bindings/dma/mtk-hsdma.txt

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MediaTek High-Speed DMA Controller
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==================================
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This device follows the generic DMA bindings defined in dma/dma.txt.
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Required properties:
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- compatible: Must be one of
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"mediatek,mt7622-hsdma": for MT7622 SoC
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"mediatek,mt7623-hsdma": for MT7623 SoC
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- reg: Should contain the register's base address and length.
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- interrupts: Should contain a reference to the interrupt used by this
13+
device.
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- clocks: Should be the clock specifiers corresponding to the entry in
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clock-names property.
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- clock-names: Should contain "hsdma" entries.
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- power-domains: Phandle to the power domain that the device is part of
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- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
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in dmas property of a client device represents the channel
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number.
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Example:
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23+
hsdma: dma-controller@1b007000 {
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compatible = "mediatek,mt7623-hsdma";
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reg = <0 0x1b007000 0 0x1000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&ethsys CLK_ETHSYS_HSDMA>;
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clock-names = "hsdma";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
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#dma-cells = <1>;
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};
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DMA clients must use the format described in dma/dma.txt file.

‎Documentation/devicetree/bindings/dma/qcom_bam_dma.txt

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@@ -15,6 +15,10 @@ Required properties:
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the secure world.
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- qcom,controlled-remotely : optional, indicates that the bam is controlled by
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remote proccessor i.e. execution environment.
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- num-channels : optional, indicates supported number of DMA channels in a
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remotely controlled bam.
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- qcom,num-ees : optional, indicates supported number of Execution Environments
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in a remotely controlled bam.
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Example:
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‎Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

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@@ -18,6 +18,7 @@ Required Properties:
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Examples with soctypes are:
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- "renesas,dmac-r8a7743" (RZ/G1M)
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- "renesas,dmac-r8a7745" (RZ/G1E)
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- "renesas,dmac-r8a77470" (RZ/G1C)
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- "renesas,dmac-r8a7790" (R-Car H2)
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- "renesas,dmac-r8a7791" (R-Car M2-W)
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- "renesas,dmac-r8a7792" (R-Car V2H)
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- "renesas,dmac-r8a7795" (R-Car H3)
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- "renesas,dmac-r8a7796" (R-Car M3-W)
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- "renesas,dmac-r8a77970" (R-Car V3M)
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- "renesas,dmac-r8a77980" (R-Car V3H)
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- reg: base address and length of the registers block for the DMAC
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‎Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt

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@@ -11,6 +11,7 @@ Required Properties:
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- "renesas,r8a7794-usb-dmac" (R-Car E2)
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- "renesas,r8a7795-usb-dmac" (R-Car H3)
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- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
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- "renesas,r8a77965-usb-dmac" (R-Car M3-N)
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- reg: base address and length of the registers block for the DMAC
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- interrupts: interrupt specifiers for the DMAC, one for each entry in
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interrupt-names.

‎Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt

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Synopsys DesignWare AXI DMA Controller
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Required properties:
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- compatible: "snps,axi-dma-1.01a"
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- reg: Address range of the DMAC registers. This should include
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all of the per-channel registers.
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- interrupt: Should contain the DMAC interrupt number.
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device.
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- dma-channels: Number of channels supported by hardware.
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- snps,dma-masters: Number of AXI masters supported by the hardware.
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- snps,data-width: Maximum AXI data width supported by hardware.
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(0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
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- snps,priority: Priority of channel. Array size is equal to the number of
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dma-channels. Priority value must be programmed within [0:dma-channels-1]
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range. (0 - minimum priority)
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- snps,block-size: Maximum block size supported by the controller channel.
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Array size is equal to the number of dma-channels.
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Optional properties:
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- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
22+
in this property. If this property is missing the maximum AXI burst length
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supported by DMAC is used. [1:256]
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Example:
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27+
dmac: dma-controller@80000 {
28+
compatible = "snps,axi-dma-1.01a";
29+
reg = <0x80000 0x400>;
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clocks = <&core_clk>, <&cfgr_clk>;
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clock-names = "core-clk", "cfgr-clk";
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interrupt-parent = <&intc>;
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interrupts = <27>;
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35+
dma-channels = <4>;
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snps,dma-masters = <2>;
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snps,data-width = <3>;
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snps,block-size = <4096 4096 4096 4096>;
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snps,priority = <0 1 2 3>;
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snps,axi-max-burst-len = <16>;
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};

‎Documentation/devicetree/bindings/dma/stm32-dma.txt

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@@ -62,14 +62,14 @@ channel: a phandle to the DMA controller plus the following four integer cells:
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0x1: medium
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0x2: high
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0x3: very high
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4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
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dependent:
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-bit 0-1: Fifo threshold
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4. A 32bit bitfield value specifying DMA features which are device dependent:
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-bit 0-1: DMA FIFO threshold selection
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0x0: 1/4 full FIFO
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0x1: 1/2 full FIFO
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0x2: 3/4 full FIFO
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0x3: full FIFO
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Example:
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usart1: serial@40011000 {

‎MAINTAINERS

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@@ -8859,6 +8859,15 @@ M: Sean Wang <[email protected]>
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S: Maintained
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F: drivers/media/rc/mtk-cir.c
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MEDIATEK DMA DRIVER
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M: Sean Wang <[email protected]>
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L: [email protected]
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L: [email protected] (moderated for non-subscribers)
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/dma/mtk-*
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F: drivers/dma/mediatek/
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MEDIATEK PMIC LED DRIVER
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M: Sean Wang <[email protected]>
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S: Maintained
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F: drivers/gpio/gpio-dwapb.c
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F: Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
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SYNOPSYS DESIGNWARE AXI DMAC DRIVER
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M: Eugeniy Paltsev <[email protected]>
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S: Maintained
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F: drivers/dma/dwi-axi-dmac/
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F: Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
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SYNOPSYS DESIGNWARE DMAC DRIVER
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M: Viresh Kumar <[email protected]>
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R: Andy Shevchenko <[email protected]>

‎drivers/dma/Kconfig

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@@ -187,6 +187,16 @@ config DMA_SUN6I
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help
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Support for the DMA engine first found in Allwinner A31 SoCs.
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config DW_AXI_DMAC
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tristate "Synopsys DesignWare AXI DMA support"
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depends on OF || COMPILE_TEST
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Enable support for Synopsys DesignWare AXI DMA controller.
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NOTE: This driver wasn't tested on 64 bit platform because
198+
of lack 64 bit platform with Synopsys DW AXI DMAC.
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config EP93XX_DMA
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bool "Cirrus Logic EP93xx DMA support"
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depends on ARCH_EP93XX || COMPILE_TEST
@@ -633,6 +643,8 @@ config ZX_DMA
633643
# driver files
634644
source "drivers/dma/bestcomm/Kconfig"
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source "drivers/dma/mediatek/Kconfig"
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source "drivers/dma/qcom/Kconfig"
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source "drivers/dma/dw/Kconfig"

‎drivers/dma/Makefile

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@@ -28,6 +28,7 @@ obj-$(CONFIG_DMA_OMAP) += omap-dma.o
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obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
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obj-$(CONFIG_DMA_SUN4I) += sun4i-dma.o
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obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
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obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
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obj-$(CONFIG_DW_DMAC_CORE) += dw/
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obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
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obj-$(CONFIG_FSL_DMA) += fsldma.o
@@ -75,5 +76,6 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
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obj-$(CONFIG_ZX_DMA) += zx_dma.o
7677
obj-$(CONFIG_ST_FDMA) += st_fdma.o
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obj-y += mediatek/
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obj-y += qcom/
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obj-y += xilinx/

‎drivers/dma/at_xdmac.c

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14711471
for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) {
14721472
check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
14731473
rmb();
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initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD);
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rmb();
14761474
cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
14771475
rmb();
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initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD);
1477+
rmb();
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cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
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rmb();
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‎drivers/dma/dmatest.c

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static bool noverify;
7676
module_param(noverify, bool, S_IRUGO | S_IWUSR);
77-
MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
77+
MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
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79+
static bool norandom;
80+
module_param(norandom, bool, 0644);
81+
MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
7882

7983
static bool verbose;
8084
module_param(verbose, bool, S_IRUGO | S_IWUSR);
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103107
unsigned int pq_sources;
104108
int timeout;
105109
bool noverify;
110+
bool norandom;
106111
};
107112

108113
/**
@@ -575,7 +580,7 @@ static int dmatest_func(void *data)
575580
break;
576581
}
577582

578-
if (params->noverify)
583+
if (params->norandom)
579584
len = params->buf_size;
580585
else
581586
len = dmatest_random() % params->buf_size + 1;
@@ -586,17 +591,19 @@ static int dmatest_func(void *data)
586591

587592
total_len += len;
588593

589-
if (params->noverify) {
594+
if (params->norandom) {
590595
src_off = 0;
591596
dst_off = 0;
592597
} else {
593-
start = ktime_get();
594598
src_off = dmatest_random() % (params->buf_size - len + 1);
595599
dst_off = dmatest_random() % (params->buf_size - len + 1);
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597601
src_off = (src_off >> align) << align;
598602
dst_off = (dst_off >> align) << align;
603+
}
599604

605+
if (!params->noverify) {
606+
start = ktime_get();
600607
dmatest_init_srcs(thread->srcs, src_off, len,
601608
params->buf_size, is_memset);
602609
dmatest_init_dsts(thread->dsts, dst_off, len,
@@ -975,6 +982,7 @@ static void run_threaded_test(struct dmatest_info *info)
975982
params->pq_sources = pq_sources;
976983
params->timeout = timeout;
977984
params->noverify = noverify;
985+
params->norandom = norandom;
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979987
request_channels(info, DMA_MEMCPY);
980988
request_channels(info, DMA_MEMSET);

‎drivers/dma/dw-axi-dmac/Makefile

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1+
obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac-platform.o

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