@@ -1538,20 +1538,25 @@ static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
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return SPECTRE_V2_RETPOLINE ;
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}
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+ static bool __ro_after_init rrsba_disabled ;
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+
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/* Disable in-kernel use of non-RSB RET predictors */
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static void __init spec_ctrl_disable_kernel_rrsba (void )
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{
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- u64 x86_arch_cap_msr ;
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+ if (rrsba_disabled )
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+ return ;
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- if (!boot_cpu_has (X86_FEATURE_RRSBA_CTRL ))
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+ if (!(x86_arch_cap_msr & ARCH_CAP_RRSBA )) {
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+ rrsba_disabled = true;
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return ;
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+ }
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- x86_arch_cap_msr = x86_read_arch_cap_msr ();
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+ if (!boot_cpu_has (X86_FEATURE_RRSBA_CTRL ))
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+ return ;
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- if (x86_arch_cap_msr & ARCH_CAP_RRSBA ) {
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- x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S ;
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- update_spec_ctrl (x86_spec_ctrl_base );
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- }
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+ x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S ;
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+ update_spec_ctrl (x86_spec_ctrl_base );
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+ rrsba_disabled = true;
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}
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static void __init spectre_v2_determine_rsb_fill_type_at_vmexit (enum spectre_v2_mitigation mode )
@@ -1652,9 +1657,11 @@ static void __init bhi_select_mitigation(void)
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return ;
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/* Retpoline mitigates against BHI unless the CPU has RRSBA behavior */
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- if (cpu_feature_enabled (X86_FEATURE_RETPOLINE ) &&
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- !(x86_read_arch_cap_msr () & ARCH_CAP_RRSBA ))
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- return ;
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+ if (cpu_feature_enabled (X86_FEATURE_RETPOLINE )) {
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+ spec_ctrl_disable_kernel_rrsba ();
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+ if (rrsba_disabled )
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+ return ;
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+ }
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if (spec_ctrl_bhi_dis ())
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return ;
@@ -2809,8 +2816,7 @@ static const char *spectre_bhi_state(void)
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return "; BHI: BHI_DIS_S" ;
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else if (boot_cpu_has (X86_FEATURE_CLEAR_BHB_LOOP ))
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return "; BHI: SW loop, KVM: SW loop" ;
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- else if (boot_cpu_has (X86_FEATURE_RETPOLINE ) &&
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- !(x86_arch_cap_msr & ARCH_CAP_RRSBA ))
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+ else if (boot_cpu_has (X86_FEATURE_RETPOLINE ) && rrsba_disabled )
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return "; BHI: Retpoline" ;
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else if (boot_cpu_has (X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT ))
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return "; BHI: Syscall hardening, KVM: SW loop" ;
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