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jpoimboeIngo Molnar
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x86/bugs: Fix BHI handling of RRSBA
The ARCH_CAP_RRSBA check isn't correct: RRSBA may have already been disabled by the Spectre v2 mitigation (or can otherwise be disabled by the BHI mitigation itself if needed). In that case retpolines are fine. Fixes: ec9404e ("x86/bhi: Add BHI mitigation knob") Signed-off-by: Josh Poimboeuf <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Sean Christopherson <[email protected]> Link: https://lore.kernel.org/r/6f56f13da34a0834b69163467449be7f58f253dc.1712813475.git.jpoimboe@kernel.org
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arch/x86/kernel/cpu/bugs.c

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1538,20 +1538,25 @@ static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
15381538
return SPECTRE_V2_RETPOLINE;
15391539
}
15401540

1541+
static bool __ro_after_init rrsba_disabled;
1542+
15411543
/* Disable in-kernel use of non-RSB RET predictors */
15421544
static void __init spec_ctrl_disable_kernel_rrsba(void)
15431545
{
1544-
u64 x86_arch_cap_msr;
1546+
if (rrsba_disabled)
1547+
return;
15451548

1546-
if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1549+
if (!(x86_arch_cap_msr & ARCH_CAP_RRSBA)) {
1550+
rrsba_disabled = true;
15471551
return;
1552+
}
15481553

1549-
x86_arch_cap_msr = x86_read_arch_cap_msr();
1554+
if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1555+
return;
15501556

1551-
if (x86_arch_cap_msr & ARCH_CAP_RRSBA) {
1552-
x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1553-
update_spec_ctrl(x86_spec_ctrl_base);
1554-
}
1557+
x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1558+
update_spec_ctrl(x86_spec_ctrl_base);
1559+
rrsba_disabled = true;
15551560
}
15561561

15571562
static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
@@ -1652,9 +1657,11 @@ static void __init bhi_select_mitigation(void)
16521657
return;
16531658

16541659
/* Retpoline mitigates against BHI unless the CPU has RRSBA behavior */
1655-
if (cpu_feature_enabled(X86_FEATURE_RETPOLINE) &&
1656-
!(x86_read_arch_cap_msr() & ARCH_CAP_RRSBA))
1657-
return;
1660+
if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
1661+
spec_ctrl_disable_kernel_rrsba();
1662+
if (rrsba_disabled)
1663+
return;
1664+
}
16581665

16591666
if (spec_ctrl_bhi_dis())
16601667
return;
@@ -2809,8 +2816,7 @@ static const char *spectre_bhi_state(void)
28092816
return "; BHI: BHI_DIS_S";
28102817
else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP))
28112818
return "; BHI: SW loop, KVM: SW loop";
2812-
else if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&
2813-
!(x86_arch_cap_msr & ARCH_CAP_RRSBA))
2819+
else if (boot_cpu_has(X86_FEATURE_RETPOLINE) && rrsba_disabled)
28142820
return "; BHI: Retpoline";
28152821
else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT))
28162822
return "; BHI: Syscall hardening, KVM: SW loop";

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