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Merge branches 'clk-airoha', 'clk-rockchip', 'clk-stm', 'clk-thead' and 'clk-bcm' into clk-next
* clk-airoha: clk: en7523: Add clock for eMMC for EN7581 dt-bindings: clock: add ID for eMMC for EN7581 dt-bindings: clock: drop NUM_CLOCKS define for EN7581 clk: en7523: Rework clock handling for different clock numbers clk: en7523: Initialize num before accessing hws in en7523_register_clocks() clk: en7523: Fix wrong BUS clock for EN7581 clk: amlogic: axg-audio: revert reset implementation Revert "clk: Fix invalid execution of clk_set_rate" * clk-rockchip: clk: rockchip: rk3588: make refclko25m_ethX critical clk: rockchip: rk3588: drop RK3588_LINKED_CLK clk: rockchip: implement linked gate clock support clk: rockchip: expose rockchip_clk_set_lookup clk: rockchip: rk3588: register GATE_LINK later clk: rockchip: support clocks registered late * clk-stm: clk: stm32f4: support spread spectrum clock generation clk: stm32f4: use FIELD helpers to access the PLLCFGR fields dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking dt-bindings: clock: convert stm32 rcc bindings to json-schema * clk-thead: clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot clk: thead: Fix clk gate registration to pass flags * clk-bcm: clk: bcm: rpi: Add disp clock clk: bcm: rpi: Create helper to retrieve private data clk: bcm: rpi: Enable minimize for all firmware clocks clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks clk: bcm: rpi: Add ISP to exported clocks
6 parents b2fee97 + bfe257f + 57ea142 + 65b3516 + 3a43cd1 + e7d0b02 commit 1d2da92

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-241
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18 files changed

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lines changed

‎Documentation/devicetree/bindings/clock/st,stm32-rcc.txt

Lines changed: 0 additions & 138 deletions
This file was deleted.

‎Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml

Lines changed: 144 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,144 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 Reset Clock Controller
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maintainers:
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- Dario Binacchi <[email protected]>
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description: |
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The RCC IP is both a reset and a clock controller.
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The reset phandle argument is the bit number within the RCC registers bank,
15+
starting from RCC base address.
16+
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- st,stm32f42xx-rcc
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- st,stm32f746-rcc
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- st,stm32h743-rcc
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- const: st,stm32-rcc
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- items:
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- enum:
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- st,stm32f469-rcc
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- const: st,stm32f42xx-rcc
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- const: st,stm32-rcc
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- items:
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- enum:
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- st,stm32f769-rcc
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- const: st,stm32f746-rcc
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- const: st,stm32-rcc
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reg:
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maxItems: 1
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'#reset-cells':
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const: 1
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'#clock-cells':
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enum: [1, 2]
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clocks:
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minItems: 2
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maxItems: 3
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st,syscfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to system configuration controller. It can be used to control the
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power domain circuitry.
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st,ssc-modfreq-hz:
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description:
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The modulation frequency for main PLL (in Hz)
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st,ssc-moddepth-permyriad:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The modulation rate for main PLL (in permyriad, i.e. 0.01%)
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minimum: 25
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maximum: 200
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st,ssc-modmethod:
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$ref: /schemas/types.yaml#/definitions/string
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description:
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The modulation techniques for main PLL.
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items:
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enum:
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- center-spread
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- down-spread
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required:
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- compatible
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- reg
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- '#reset-cells'
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- '#clock-cells'
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- clocks
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- st,syscfg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32h743-rcc
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then:
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properties:
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'#clock-cells':
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const: 1
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description: |
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The clock index for the specified type.
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clocks:
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items:
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- description: high speed external (HSE) clock input
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- description: low speed external (LSE) clock input
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- description: Inter-IC sound (I2S) clock input
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st,ssc-modfreq-hz: false
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st,ssc-moddepth-permyriad: false
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st,ssc-modmethod: false
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else:
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properties:
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'#clock-cells':
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const: 2
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description: |
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- The first cell is the clock type, possible values are 0 for
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gated clocks and 1 otherwise.
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- The second cell is the clock index for the specified type.
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clocks:
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items:
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- description: high speed external (HSE) clock input
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- description: Inter-IC sound (I2S) clock input
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additionalProperties: false
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examples:
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# Reset and Clock Control Module node:
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- |
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clock-controller@40023800 {
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compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
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reg = <0x40023800 0x400>;
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#clock-cells = <2>;
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#reset-cells = <1>;
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clocks = <&clk_hse>, <&clk_i2s_ckin>;
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st,syscfg = <&pwrcfg>;
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st,ssc-modfreq-hz = <10000>;
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st,ssc-moddepth-permyriad = <200>;
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st,ssc-modmethod = "center-spread";
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};
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- |
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clock-controller@58024400 {
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compatible = "st,stm32h743-rcc", "st,stm32-rcc";
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reg = <0x58024400 0x400>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
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st,syscfg = <&pwrcfg>;
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};
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...

‎Documentation/devicetree/bindings/reset/st,stm32-rcc.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,4 +3,4 @@ STMicroelectronics STM32 Peripheral Reset Controller
33

44
The RCC IP is both a reset and a clock controller.
55

6-
Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
6+
Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml

‎drivers/clk/bcm/clk-raspberrypi.c

Lines changed: 24 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ static char *rpi_firmware_clk_names[] = {
3434
[RPI_FIRMWARE_M2MC_CLK_ID] = "m2mc",
3535
[RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = "pixel-bvb",
3636
[RPI_FIRMWARE_VEC_CLK_ID] = "vec",
37+
[RPI_FIRMWARE_DISP_CLK_ID] = "disp",
3738
};
3839

3940
#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
@@ -56,6 +57,12 @@ struct raspberrypi_clk_data {
5657
struct raspberrypi_clk *rpi;
5758
};
5859

60+
static inline
61+
const struct raspberrypi_clk_data *clk_hw_to_data(const struct clk_hw *hw)
62+
{
63+
return container_of(hw, struct raspberrypi_clk_data, hw);
64+
}
65+
5966
struct raspberrypi_clk_variant {
6067
bool export;
6168
char *clkdev;
@@ -111,18 +118,31 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
111118
},
112119
[RPI_FIRMWARE_V3D_CLK_ID] = {
113120
.export = true,
121+
.minimize = true,
114122
},
115123
[RPI_FIRMWARE_PIXEL_CLK_ID] = {
116124
.export = true,
125+
.minimize = true,
117126
},
118127
[RPI_FIRMWARE_HEVC_CLK_ID] = {
119128
.export = true,
129+
.minimize = true,
130+
},
131+
[RPI_FIRMWARE_ISP_CLK_ID] = {
132+
.export = true,
133+
.minimize = true,
120134
},
121135
[RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = {
122136
.export = true,
137+
.minimize = true,
123138
},
124139
[RPI_FIRMWARE_VEC_CLK_ID] = {
125140
.export = true,
141+
.minimize = true,
142+
},
143+
[RPI_FIRMWARE_DISP_CLK_ID] = {
144+
.export = true,
145+
.minimize = true,
126146
},
127147
};
128148

@@ -153,7 +173,6 @@ static int raspberrypi_clock_property(struct rpi_firmware *firmware,
153173
struct raspberrypi_firmware_prop msg = {
154174
.id = cpu_to_le32(data->id),
155175
.val = cpu_to_le32(*val),
156-
.disable_turbo = cpu_to_le32(1),
157176
};
158177
int ret;
159178

@@ -168,8 +187,7 @@ static int raspberrypi_clock_property(struct rpi_firmware *firmware,
168187

169188
static int raspberrypi_fw_is_prepared(struct clk_hw *hw)
170189
{
171-
struct raspberrypi_clk_data *data =
172-
container_of(hw, struct raspberrypi_clk_data, hw);
190+
const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
173191
struct raspberrypi_clk *rpi = data->rpi;
174192
u32 val = 0;
175193
int ret;
@@ -186,8 +204,7 @@ static int raspberrypi_fw_is_prepared(struct clk_hw *hw)
186204
static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
187205
unsigned long parent_rate)
188206
{
189-
struct raspberrypi_clk_data *data =
190-
container_of(hw, struct raspberrypi_clk_data, hw);
207+
const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
191208
struct raspberrypi_clk *rpi = data->rpi;
192209
u32 val = 0;
193210
int ret;
@@ -203,8 +220,7 @@ static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
203220
static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
204221
unsigned long parent_rate)
205222
{
206-
struct raspberrypi_clk_data *data =
207-
container_of(hw, struct raspberrypi_clk_data, hw);
223+
const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
208224
struct raspberrypi_clk *rpi = data->rpi;
209225
u32 _rate = rate;
210226
int ret;
@@ -221,8 +237,7 @@ static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
221237
static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw,
222238
struct clk_rate_request *req)
223239
{
224-
struct raspberrypi_clk_data *data =
225-
container_of(hw, struct raspberrypi_clk_data, hw);
240+
const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
226241
struct raspberrypi_clk_variant *variant = data->variant;
227242

228243
/*

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