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Matt Carlsondavem330
Matt Carlson
authored and
davem330
committed
tg3: Add macro for SMDSP toggling
A common AUX CTRL operation in the driver is to enable and disable the SMDSP. This patch consolidates the code so that the details of the operation are in one place. This patch also adds code to make sure the SMDSP is enabled before executing code that relies on it. Signed-off-by: Matt Carlson <[email protected]> Reviewed-by: Michael Chan <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/tg3.c

Lines changed: 46 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -970,6 +970,15 @@ static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
970970
return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
971971
}
972972

973+
#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
974+
tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
975+
MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
976+
MII_TG3_AUXCTL_ACTL_TX_6DB)
977+
978+
#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
979+
tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
980+
MII_TG3_AUXCTL_ACTL_TX_6DB);
981+
973982
static int tg3_bmcr_reset(struct tg3 *tp)
974983
{
975984
u32 phy_control;
@@ -1738,11 +1747,8 @@ static void tg3_phy_apply_otp(struct tg3 *tp)
17381747

17391748
otp = tp->phy_otp;
17401749

1741-
/* Enable SM_DSP clock and tx 6dB coding. */
1742-
phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1743-
MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1744-
MII_TG3_AUXCTL_ACTL_TX_6DB;
1745-
tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1750+
if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
1751+
return;
17461752

17471753
phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
17481754
phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
@@ -1766,10 +1772,7 @@ static void tg3_phy_apply_otp(struct tg3 *tp)
17661772
((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
17671773
tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
17681774

1769-
/* Turn off SM_DSP clock. */
1770-
phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1771-
MII_TG3_AUXCTL_ACTL_TX_6DB;
1772-
tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1775+
TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
17731776
}
17741777

17751778
static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
@@ -1804,18 +1807,11 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
18041807
case ASIC_REV_5717:
18051808
case ASIC_REV_5719:
18061809
case ASIC_REV_57765:
1807-
/* Enable SM_DSP clock and tx 6dB coding. */
1808-
val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1809-
MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1810-
MII_TG3_AUXCTL_ACTL_TX_6DB;
1811-
tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1812-
1813-
tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1814-
1815-
/* Turn off SM_DSP clock. */
1816-
val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1817-
MII_TG3_AUXCTL_ACTL_TX_6DB;
1818-
tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1810+
if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
1811+
tg3_phydsp_write(tp, MII_TG3_DSP_TAP26,
1812+
0x0000);
1813+
TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1814+
}
18191815
}
18201816
/* Fallthrough */
18211817
case TG3_CL45_D7_EEERES_STAT_LP_100TX:
@@ -1967,8 +1963,9 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
19671963
(MII_TG3_CTRL_AS_MASTER |
19681964
MII_TG3_CTRL_ENABLE_AS_MASTER));
19691965

1970-
/* Enable SM_DSP_CLOCK and 6dB. */
1971-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966+
err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
1967+
if (err)
1968+
return err;
19721969

19731970
/* Block the PHY control access. */
19741971
tg3_phydsp_write(tp, 0x8005, 0x0800);
@@ -1987,13 +1984,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
19871984
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
19881985
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
19891986

1990-
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1991-
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1992-
/* Set Extended packet length bit for jumbo frames */
1993-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1994-
} else {
1995-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1996-
}
1987+
TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
19971988

19981989
tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
19991990

@@ -2081,33 +2072,39 @@ static int tg3_phy_reset(struct tg3 *tp)
20812072
tg3_phy_toggle_apd(tp, false);
20822073

20832074
out:
2084-
if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2085-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2075+
if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2076+
!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
20862077
tg3_phydsp_write(tp, 0x201f, 0x2aaa);
20872078
tg3_phydsp_write(tp, 0x000a, 0x0323);
2088-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2079+
TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
20892080
}
2081+
20902082
if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
20912083
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
20922084
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
20932085
}
2086+
20942087
if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2095-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2096-
tg3_phydsp_write(tp, 0x000a, 0x310b);
2097-
tg3_phydsp_write(tp, 0x201f, 0x9506);
2098-
tg3_phydsp_write(tp, 0x401f, 0x14e2);
2099-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2088+
if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2089+
tg3_phydsp_write(tp, 0x000a, 0x310b);
2090+
tg3_phydsp_write(tp, 0x201f, 0x9506);
2091+
tg3_phydsp_write(tp, 0x401f, 0x14e2);
2092+
TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2093+
}
21002094
} else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2101-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2102-
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2103-
if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2104-
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2105-
tg3_writephy(tp, MII_TG3_TEST1,
2106-
MII_TG3_TEST1_TRIM_EN | 0x4);
2107-
} else
2108-
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2109-
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2095+
if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2096+
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2097+
if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2098+
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2099+
tg3_writephy(tp, MII_TG3_TEST1,
2100+
MII_TG3_TEST1_TRIM_EN | 0x4);
2101+
} else
2102+
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2103+
2104+
TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2105+
}
21102106
}
2107+
21112108
/* Set Extended packet length bit (bit 14) on all chips that */
21122109
/* support jumbo frames */
21132110
if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
@@ -3011,11 +3008,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
30113008
tw32(TG3_CPMU_EEE_MODE,
30123009
tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
30133010

3014-
/* Enable SM_DSP clock and tx 6dB coding. */
3015-
val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3016-
MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
3017-
MII_TG3_AUXCTL_ACTL_TX_6DB;
3018-
tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3011+
TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
30193012

30203013
switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
30213014
case ASIC_REV_5717:
@@ -3044,10 +3037,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
30443037
}
30453038
tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
30463039

3047-
/* Turn off SM_DSP clock. */
3048-
val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3049-
MII_TG3_AUXCTL_ACTL_TX_6DB;
3050-
tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3040+
TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
30513041
}
30523042

30533043
if (tp->link_config.autoneg == AUTONEG_DISABLE &&

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