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torvaldstorvalds
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon/kms: fix channel_remap setup (v2) drm/radeon: Set cursor x/y to 0 when x/yorigin > 0. drm/radeon: Update AVIVO cursor coordinate origin before x/yorigin calculation. drm/radeon: Simplify cursor x/yorigin calculation. drm/radeon/kms: fix cursor image off-by-one error drm/radeon/kms: Fix logic error in DP HPD handler drm/radeon/kms: add retry limits for native DP aux defer drm/radeon/kms: fix regression in DP aux defer handling
2 parents f8451c3 + 12d5180 commit 1fd2a85

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6 files changed

+33
-158
lines changed

6 files changed

+33
-158
lines changed

‎drivers/gpu/drm/radeon/atombios_dp.c

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
115115
u8 msg[20];
116116
int msg_bytes = send_bytes + 4;
117117
u8 ack;
118+
unsigned retry;
118119

119120
if (send_bytes > 16)
120121
return -1;
@@ -125,20 +126,20 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
125126
msg[3] = (msg_bytes << 4) | (send_bytes - 1);
126127
memcpy(&msg[4], send, send_bytes);
127128

128-
while (1) {
129+
for (retry = 0; retry < 4; retry++) {
129130
ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
130131
msg, msg_bytes, NULL, 0, delay, &ack);
131132
if (ret < 0)
132133
return ret;
133134
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
134-
break;
135+
return send_bytes;
135136
else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
136137
udelay(400);
137138
else
138139
return -EIO;
139140
}
140141

141-
return send_bytes;
142+
return -EIO;
142143
}
143144

144145
static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
@@ -149,26 +150,29 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
149150
int msg_bytes = 4;
150151
u8 ack;
151152
int ret;
153+
unsigned retry;
152154

153155
msg[0] = address;
154156
msg[1] = address >> 8;
155157
msg[2] = AUX_NATIVE_READ << 4;
156158
msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
157159

158-
while (1) {
160+
for (retry = 0; retry < 4; retry++) {
159161
ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
160162
msg, msg_bytes, recv, recv_bytes, delay, &ack);
161-
if (ret == 0)
162-
return -EPROTO;
163163
if (ret < 0)
164164
return ret;
165165
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
166166
return ret;
167167
else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
168168
udelay(400);
169+
else if (ret == 0)
170+
return -EPROTO;
169171
else
170172
return -EIO;
171173
}
174+
175+
return -EIO;
172176
}
173177

174178
static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,

‎drivers/gpu/drm/radeon/evergreen.c

Lines changed: 0 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
15901590
return backend_map;
15911591
}
15921592

1593-
static void evergreen_program_channel_remap(struct radeon_device *rdev)
1594-
{
1595-
u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1596-
1597-
tmp = RREG32(MC_SHARED_CHMAP);
1598-
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1599-
case 0:
1600-
case 1:
1601-
case 2:
1602-
case 3:
1603-
default:
1604-
/* default mapping */
1605-
mc_shared_chremap = 0x00fac688;
1606-
break;
1607-
}
1608-
1609-
switch (rdev->family) {
1610-
case CHIP_HEMLOCK:
1611-
case CHIP_CYPRESS:
1612-
case CHIP_BARTS:
1613-
tcp_chan_steer_lo = 0x54763210;
1614-
tcp_chan_steer_hi = 0x0000ba98;
1615-
break;
1616-
case CHIP_JUNIPER:
1617-
case CHIP_REDWOOD:
1618-
case CHIP_CEDAR:
1619-
case CHIP_PALM:
1620-
case CHIP_SUMO:
1621-
case CHIP_SUMO2:
1622-
case CHIP_TURKS:
1623-
case CHIP_CAICOS:
1624-
default:
1625-
tcp_chan_steer_lo = 0x76543210;
1626-
tcp_chan_steer_hi = 0x0000ba98;
1627-
break;
1628-
}
1629-
1630-
WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1631-
WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1632-
WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1633-
}
1634-
16351593
static void evergreen_gpu_init(struct radeon_device *rdev)
16361594
{
16371595
u32 cc_rb_backend_disable = 0;
@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
20782036
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
20792037
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
20802038

2081-
evergreen_program_channel_remap(rdev);
2082-
20832039
num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
20842040
grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
20852041

‎drivers/gpu/drm/radeon/ni.c

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
569569
return backend_map;
570570
}
571571

572-
static void cayman_program_channel_remap(struct radeon_device *rdev)
573-
{
574-
u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
575-
576-
tmp = RREG32(MC_SHARED_CHMAP);
577-
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
578-
case 0:
579-
case 1:
580-
case 2:
581-
case 3:
582-
default:
583-
/* default mapping */
584-
mc_shared_chremap = 0x00fac688;
585-
break;
586-
}
587-
588-
switch (rdev->family) {
589-
case CHIP_CAYMAN:
590-
default:
591-
//tcp_chan_steer_lo = 0x54763210
592-
tcp_chan_steer_lo = 0x76543210;
593-
tcp_chan_steer_hi = 0x0000ba98;
594-
break;
595-
}
596-
597-
WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
598-
WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
599-
WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
600-
}
601-
602572
static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
603573
u32 disable_mask_per_se,
604574
u32 max_disable_mask_per_se,
@@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
842812
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
843813
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
844814

845-
cayman_program_channel_remap(rdev);
846-
847815
/* primary versions */
848816
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
849817
WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);

‎drivers/gpu/drm/radeon/radeon_connectors.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm_connector *connector)
6868
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6969
int saved_dpms = connector->dpms;
7070

71-
if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
72-
radeon_dp_needs_link_train(radeon_connector))
73-
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
74-
else
71+
/* Only turn off the display it it's physically disconnected */
72+
if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
7573
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
74+
else if (radeon_dp_needs_link_train(radeon_connector))
75+
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
7676
connector->dpms = saved_dpms;
7777
}
7878
}

‎drivers/gpu/drm/radeon/radeon_cursor.c

Lines changed: 19 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -208,23 +208,25 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
208208
int xorigin = 0, yorigin = 0;
209209
int w = radeon_crtc->cursor_width;
210210

211-
if (x < 0)
212-
xorigin = -x + 1;
213-
if (y < 0)
214-
yorigin = -y + 1;
215-
if (xorigin >= CURSOR_WIDTH)
216-
xorigin = CURSOR_WIDTH - 1;
217-
if (yorigin >= CURSOR_HEIGHT)
218-
yorigin = CURSOR_HEIGHT - 1;
219-
220211
if (ASIC_IS_AVIVO(rdev)) {
221-
int i = 0;
222-
struct drm_crtc *crtc_p;
223-
224212
/* avivo cursor are offset into the total surface */
225213
x += crtc->x;
226214
y += crtc->y;
227-
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
215+
}
216+
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
217+
218+
if (x < 0) {
219+
xorigin = min(-x, CURSOR_WIDTH - 1);
220+
x = 0;
221+
}
222+
if (y < 0) {
223+
yorigin = min(-y, CURSOR_HEIGHT - 1);
224+
y = 0;
225+
}
226+
227+
if (ASIC_IS_AVIVO(rdev)) {
228+
int i = 0;
229+
struct drm_crtc *crtc_p;
228230

229231
/* avivo cursor image can't end on 128 pixel boundary or
230232
* go past the end of the frame if both crtcs are enabled
@@ -253,16 +255,12 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
253255

254256
radeon_lock_cursor(crtc, true);
255257
if (ASIC_IS_DCE4(rdev)) {
256-
WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
257-
((xorigin ? 0 : x) << 16) |
258-
(yorigin ? 0 : y));
258+
WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
259259
WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
260260
WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
261261
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
262262
} else if (ASIC_IS_AVIVO(rdev)) {
263-
WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
264-
((xorigin ? 0 : x) << 16) |
265-
(yorigin ? 0 : y));
263+
WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
266264
WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
267265
WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
268266
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
@@ -276,8 +274,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
276274
| yorigin));
277275
WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
278276
(RADEON_CUR_LOCK
279-
| ((xorigin ? 0 : x) << 16)
280-
| (yorigin ? 0 : y)));
277+
| (x << 16)
278+
| y));
281279
/* offset is from DISP(2)_BASE_ADDRESS */
282280
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
283281
(yorigin * 256)));

‎drivers/gpu/drm/radeon/rv770.c

Lines changed: 0 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
536536
return backend_map;
537537
}
538538

539-
static void rv770_program_channel_remap(struct radeon_device *rdev)
540-
{
541-
u32 tcp_chan_steer, mc_shared_chremap, tmp;
542-
bool force_no_swizzle;
543-
544-
switch (rdev->family) {
545-
case CHIP_RV770:
546-
case CHIP_RV730:
547-
force_no_swizzle = false;
548-
break;
549-
case CHIP_RV710:
550-
case CHIP_RV740:
551-
default:
552-
force_no_swizzle = true;
553-
break;
554-
}
555-
556-
tmp = RREG32(MC_SHARED_CHMAP);
557-
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
558-
case 0:
559-
case 1:
560-
default:
561-
/* default mapping */
562-
mc_shared_chremap = 0x00fac688;
563-
break;
564-
case 2:
565-
case 3:
566-
if (force_no_swizzle)
567-
mc_shared_chremap = 0x00fac688;
568-
else
569-
mc_shared_chremap = 0x00bbc298;
570-
break;
571-
}
572-
573-
if (rdev->family == CHIP_RV740)
574-
tcp_chan_steer = 0x00ef2a60;
575-
else
576-
tcp_chan_steer = 0x00fac688;
577-
578-
/* RV770 CE has special chremap setup */
579-
if (rdev->pdev->device == 0x944e) {
580-
tcp_chan_steer = 0x00b08b08;
581-
mc_shared_chremap = 0x00b08b08;
582-
}
583-
584-
WREG32(TCP_CHAN_STEER, tcp_chan_steer);
585-
WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
586-
}
587-
588539
static void rv770_gpu_init(struct radeon_device *rdev)
589540
{
590541
int i, j, num_qd_pipes;
@@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
785736
WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
786737
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
787738

788-
rv770_program_channel_remap(rdev);
789-
790739
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
791740
WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
792741
WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);

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