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jbeulichKAGA-KOKO
jbeulich
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KAGA-KOKO
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x86/asm: Add instruction suffixes to bitops
Omitting suffixes from instructions in AT&T mode is bad practice when operand size cannot be determined by the assembler from register operands, and is likely going to be warned about by upstream gas in the future (mine does already). Add the missing suffixes here. Note that for 64-bit this means some operations change from being 32-bit to 64-bit. Signed-off-by: Jan Beulich <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
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-14
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+17
-14
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‎arch/x86/include/asm/bitops.h

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ set_bit(long nr, volatile unsigned long *addr)
7878
: "iq" ((u8)CONST_MASK(nr))
7979
: "memory");
8080
} else {
81-
asm volatile(LOCK_PREFIX "bts %1,%0"
81+
asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
8282
: BITOP_ADDR(addr) : "Ir" (nr) : "memory");
8383
}
8484
}
@@ -94,7 +94,7 @@ set_bit(long nr, volatile unsigned long *addr)
9494
*/
9595
static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
9696
{
97-
asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
97+
asm volatile(__ASM_SIZE(bts) " %1,%0" : ADDR : "Ir" (nr) : "memory");
9898
}
9999

100100
/**
@@ -115,7 +115,7 @@ clear_bit(long nr, volatile unsigned long *addr)
115115
: CONST_MASK_ADDR(nr, addr)
116116
: "iq" ((u8)~CONST_MASK(nr)));
117117
} else {
118-
asm volatile(LOCK_PREFIX "btr %1,%0"
118+
asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
119119
: BITOP_ADDR(addr)
120120
: "Ir" (nr));
121121
}
@@ -137,7 +137,7 @@ static __always_inline void clear_bit_unlock(long nr, volatile unsigned long *ad
137137

138138
static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
139139
{
140-
asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
140+
asm volatile(__ASM_SIZE(btr) " %1,%0" : ADDR : "Ir" (nr));
141141
}
142142

143143
static __always_inline bool clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
@@ -182,7 +182,7 @@ static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *
182182
*/
183183
static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
184184
{
185-
asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
185+
asm volatile(__ASM_SIZE(btc) " %1,%0" : ADDR : "Ir" (nr));
186186
}
187187

188188
/**
@@ -201,7 +201,7 @@ static __always_inline void change_bit(long nr, volatile unsigned long *addr)
201201
: CONST_MASK_ADDR(nr, addr)
202202
: "iq" ((u8)CONST_MASK(nr)));
203203
} else {
204-
asm volatile(LOCK_PREFIX "btc %1,%0"
204+
asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
205205
: BITOP_ADDR(addr)
206206
: "Ir" (nr));
207207
}
@@ -217,7 +217,8 @@ static __always_inline void change_bit(long nr, volatile unsigned long *addr)
217217
*/
218218
static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
219219
{
220-
GEN_BINARY_RMWcc(LOCK_PREFIX "bts", *addr, "Ir", nr, "%0", c);
220+
GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts),
221+
*addr, "Ir", nr, "%0", c);
221222
}
222223

223224
/**
@@ -246,7 +247,7 @@ static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *
246247
{
247248
bool oldbit;
248249

249-
asm("bts %2,%1"
250+
asm(__ASM_SIZE(bts) " %2,%1"
250251
CC_SET(c)
251252
: CC_OUT(c) (oldbit), ADDR
252253
: "Ir" (nr));
@@ -263,7 +264,8 @@ static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *
263264
*/
264265
static __always_inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
265266
{
266-
GEN_BINARY_RMWcc(LOCK_PREFIX "btr", *addr, "Ir", nr, "%0", c);
267+
GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr),
268+
*addr, "Ir", nr, "%0", c);
267269
}
268270

269271
/**
@@ -286,7 +288,7 @@ static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long
286288
{
287289
bool oldbit;
288290

289-
asm volatile("btr %2,%1"
291+
asm volatile(__ASM_SIZE(btr) " %2,%1"
290292
CC_SET(c)
291293
: CC_OUT(c) (oldbit), ADDR
292294
: "Ir" (nr));
@@ -298,7 +300,7 @@ static __always_inline bool __test_and_change_bit(long nr, volatile unsigned lon
298300
{
299301
bool oldbit;
300302

301-
asm volatile("btc %2,%1"
303+
asm volatile(__ASM_SIZE(btc) " %2,%1"
302304
CC_SET(c)
303305
: CC_OUT(c) (oldbit), ADDR
304306
: "Ir" (nr) : "memory");
@@ -316,7 +318,8 @@ static __always_inline bool __test_and_change_bit(long nr, volatile unsigned lon
316318
*/
317319
static __always_inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
318320
{
319-
GEN_BINARY_RMWcc(LOCK_PREFIX "btc", *addr, "Ir", nr, "%0", c);
321+
GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc),
322+
*addr, "Ir", nr, "%0", c);
320323
}
321324

322325
static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
@@ -329,7 +332,7 @@ static __always_inline bool variable_test_bit(long nr, volatile const unsigned l
329332
{
330333
bool oldbit;
331334

332-
asm volatile("bt %2,%1"
335+
asm volatile(__ASM_SIZE(bt) " %2,%1"
333336
CC_SET(c)
334337
: CC_OUT(c) (oldbit)
335338
: "m" (*(unsigned long *)addr), "Ir" (nr));

‎arch/x86/include/asm/percpu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -526,7 +526,7 @@ static inline bool x86_this_cpu_variable_test_bit(int nr,
526526
{
527527
bool oldbit;
528528

529-
asm volatile("bt "__percpu_arg(2)",%1"
529+
asm volatile("btl "__percpu_arg(2)",%1"
530530
CC_SET(c)
531531
: CC_OUT(c) (oldbit)
532532
: "m" (*(unsigned long __percpu *)addr), "Ir" (nr));

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