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TinaZhangZWjoergroedel
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iommu/vt-d: Preset Access bit for IOVA in FL non-leaf paging entries
The A/D bits are preseted for IOVA over first level(FL) usage for both kernel DMA (i.e, domain typs is IOMMU_DOMAIN_DMA) and user space DMA usage (i.e., domain type is IOMMU_DOMAIN_UNMANAGED). Presetting A bit in FL requires to preset the bit in every related paging entries, including the non-leaf ones. Otherwise, hardware may treat this as an error. For example, in a case of ECAP_REG.SMPWC==0, DMA faults might occur with below DMAR fault messages (wrapped for line length) dumped. DMAR: DRHD: handling fault status reg 2 DMAR: [DMA Read NO_PASID] Request device [aa:00.0] fault addr 0x10c3a6000 [fault reason 0x90] SM: A/D bit update needed in first-level entry when set up in no snoop Fixes: 289b3b0 ("iommu/vt-d: Preset A/D bits for user space DMA usage") Cc: [email protected] Signed-off-by: Tina Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lu Baolu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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drivers/iommu/intel/iommu.c

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -959,11 +959,9 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
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domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
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pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
962-
if (domain_use_first_level(domain)) {
963-
pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
964-
if (iommu_is_dma_domain(&domain->domain))
965-
pteval |= DMA_FL_PTE_ACCESS;
966-
}
962+
if (domain_use_first_level(domain))
963+
pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;
964+
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if (cmpxchg64(&pte->val, 0ULL, pteval))
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/* Someone else set it while we were thinking; use theirs. */
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free_pgtable_page(tmp_page);

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