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Yunsheng Lindavem330
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net: hns3: fix for vport->bw_limit overflow problem
When setting vport->bw_limit to hdev->tm_info.pg_info[0].bw_limit in hclge_tm_vport_tc_info_update, vport->bw_limit can be as big as HCLGE_ETHER_MAX_RATE (100000), which can not fit into u16 (65535). So this patch fixes it by using u32 for vport->bw_limit. Fixes: 8484405 ("net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver") Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Yunsheng Lin <[email protected]> Signed-off-by: Huazhong Tan <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -854,7 +854,7 @@ struct hclge_vport {
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u16 alloc_rss_size;
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u16 qs_offset;
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u16 bw_limit; /* VSI BW Limit (0 = disabled) */
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u32 bw_limit; /* VSI BW Limit (0 = disabled) */
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u8 dwrr;
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struct hclge_port_base_vlan_config port_base_vlan_cfg;

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